3/29 SOC Physical Design Engineer-台南
- 智原科技股份有限公司
- 半導體製造業
- 台南市永康區
- 3年以上
- 大學
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.