Minimum qualifications:
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with physical design verification flows and methodology (e.g., DRC, LVS, PERC, ESD signoff, ERC, antenna, DFM) using industry standard signoff tools.
• Experience managing various physical verification check runsets.
Preferred qualifications:
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience on full chip physical verification and bring up on physical verification methodology for correct by construction strategies.
• Experience on physical verification signoff of a SOC/sub-systems/SSWRPs.
• Experience with physical signoff verification tools (e.g., calibre and ICV).
• Experience scripting with Tcl, Perl, or Shell.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
• Use analytical and simulation techniques to ensure physical verification strategies for enabling better QoR, runtimes, and performance within defined requirements.
• Collaborate with cross-functional teams to debug performance shortfalls, program goals for physical verification methodologies, and signoff of SOCs.
• Design physical verification methodologies for chips, chip-subsystems, or partitions within subsystems for physical verification checks done through Place and Route, and establish physical sign off convergence, ensuring that the design meets the physical signoff quality.
• Develop, validate, and improve electronic design automation (EDA) methodology for a physical verification sign off to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
