5/13 (竹南)設備助理工程師-做二休二
- 瑞譜科技股份有限公司
- 其他半導體相關業
- 苗栗縣竹南鎮
- 經歷不拘
- 高中
1.工作性質:從事機器設備保養,維護清潔、品項填充與汰品更換,巡檢,接受現場工程師指派事項等。 2.需穿著無塵服 做二休二早班(10H):07:30-19:30 做二休二晚班(10H):19:30-07:30 需輪早晚班,每三個月,日班及晚班輪替。.
1.工作性質:從事機器設備保養,維護清潔、品項填充與汰品更換,巡檢,接受現場工程師指派事項等。 2.需穿著無塵服 做二休二早班(10H):07:30-19:30 做二休二晚班(10H):19:30-07:30 需輪早晚班,每三個月,日班及晚班輪替。.
工作性質: 1.從事機台保養、更換耗材、清潔零件、量測、拍照,接受現場工程師指派事項等。 2.工作上須能搬重物。 3.需輪早晚班,每三個月日夜輪班一次。. (做二休二早班(10H):07:30-19:30,做二休二晚班(10H):19:30-07:30) 4.需穿著無塵服。
工作性質: 1.工作性質:機器設備保養維護清潔、更換耗材、清潔零件等工作, 接受現場工程師指派事項等。 2.上班時間:做二休二早班(10H):07:30-19:30及做二休二晚班(10H):19:30-07:30, 需輪早班及晚班,每三個月日夜輪班一次。 3.須穿著無塵服。
工作性質: 1.工作性質:機器設備保養維護清潔、更換耗材、清潔零件等工作, 接受現場工程師指派事項等。 2.上班時間為日班:07:30AM-19:30PM(做二休二 日班)。 3.需排班。 4.須穿著無塵服。
• Provide SI/PI support to local & overseas field application engineers to ensure customer board performance • Review customer board layout & schematics for SI design rule compliance and power rail decoupling • Collaborate with PCB layout engineers to design & optimize test boards • Perform board-level EM simulations to optimize interconnects for impedance, skew, and crosstalk • Conduct IR drop & Z(f) analyses to confirm power distribution network (PDN) performance • Develop package substrate & PCB design guidelines for customers
1. Analog circuit design and verification, such as OPAMP, Bandgap, ADC/DAC, PLL, and etc. 2. Power management circuit design and verification, such as LDOs, Charge Pumps, Switching Regulators, Gamma reference, and etc. 3. Whole chip integration with mixed-signal circuit. 4. HV I/O and ESD design.
1. Responsible for display and image processing algorithm development. 2. Participate in system architecture definition, algorithm developing and evaluation, algorithm implementation and simulation.
-Solid integrated circuit and solid state devices knowledge -Familiar with circuit design EDA tools -Knowledges in the following areas are a plus: PLL, high speed circuit design, I/O design, LVDS, ESD, ADC/DAC, switching regulator, low noise design
1. In charge of implementing digital circuits for mixed-signal design (from gate level netlist to GDS) 2. Performing daily tasks including floor-plan, CTS, PnR, STA, Power budget, IR-drop / EM / Cross-talking analysis and sign-off. 3. Estimation of efforts and schedules for assigned project. 4. Close cooperation and interaction with other design teams in different company sites.
-Solid integrated circuit and solid state devices knowledge -Familiar with circuit design EDA tools -Knowledges in the following areas are a plus: PLL, high speed circuit design, I/O design, LVDS, ESD, ADC/DAC, switching regulator, low noise design
• Provide SI/PI support to local & overseas field application engineers to ensure customer board performance • Review customer board layout & schematics for SI design rule compliance and power rail decoupling • Collaborate with PCB layout engineers to design & optimize test boards • Perform board-level EM simulations to optimize interconnects for impedance, skew, and crosstalk • Conduct IR drop & Z(f) analyses to confirm power distribution network (PDN) performance • Develop package substrate & PCB design guidelines for customers
1. 5+ years experiences with MS in EE 2. Hands on experiences on the design and validation of wireline high speed silicon 3. Experiences with strong design capability for the 10Gbps+ wireline data transfer 4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus
1. Partnership and reference design engagement 2. Engage with key OEM/ODM customer and major SOC vendors to define new products in high speed area. 3. Work with cross-functioning team from define phase to POC phase, design-in phase, then achieving mass production. 4. Coordinating cross department and multi-functional teams. 5. Promotion activity, plan, prepare and deliver presentations. 6. Collect market data and conduct competitive analysis from field side.
1. 5+ years’ experience with MS or PHD in EE. 2. Familiar with BJT circuit design. 3. Experience in these areas is preferred: BiCMOS, CMOS or SiGe high-speed (>10Gb/s) circuit, Linear electrical amplifier & equalizer, limiting amplifier, and CML/SST driver.
1. 5+ years experiences with MS in EE 2. Hands on experiences on the design and validation of wireline high speed silicon 3. Experiences with strong design capability for the 10Gbps+ wireline data transfer 4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus
1. Work with mixed signal design team to create behavioral models for complex circuits 2. Work with design team to optimize circuits or system architecture to meet design specifications 3. Verify system level performance and functionality of high speed SERDES ICs 4. Validate silicon performance and correlate results with models
1. Work with mixed signal design team to create behavioral models for complex circuits 2. Work with design team to optimize circuits or system architecture to meet design specifications 3. Verify system level performance and functionality of high speed SERDES ICs 4. Validate silicon performance and correlate results with models
1. 5+ years’ experience with MS or PHD in EE. 2. Familiar with BJT circuit design. 3. Experience in these areas is preferred: BiCMOS, CMOS or SiGe high-speed (>10Gb/s) circuit, Linear electrical amplifier & equalizer, limiting amplifier, and CML/SST driver.
1. Analog circuit design and verification, such as OPAMP, Bandgap, ADC/DAC, PLL, and etc. 2. Power management circuit design and verification, such as LDOs, Charge Pumps, Switching Regulators, Gamma reference, and etc. 3. Whole chip integration with mixed-signal circuit. 4. HV I/O and ESD design.
1. Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board 2. Support Customer projects design-in stage to mass-production. 3. Support Customer projects design review (Schematics, layout, CTS report) 4. Team work with RD, AE and QA on debugging and problems solve.