4/25 Algorithm IP RTL designer and architect
- 晶錡微電子股份有限公司
- 電腦軟體服務業
- 台北市內湖區
- 3年以上
- 大學
fixed-point algorithm and cost reduction algorithm developing. 4.Familiar with SystemC to RTL flow is plus.
fixed-point algorithm and cost reduction algorithm developing. 4.Familiar with SystemC to RTL flow is plus.
-About 艾盟仕- 國際品牌的營銷夥伴,給予多國在地品牌總代理(台灣、大陸、越南)銷售管理服務。 包括運動系列專業團隊, 快速成長的年輕團隊,邀您一同攜手開拓。 1. 會議資料整理、進度追蹤跟進。 2. 銷貨作業執行。 3. 資料蒐集及競品資料整理。 4. 協助各項專案推動、監控及執行。 5. 部門員工活動規劃與執行。 6. 完成主管交辦事務。
1. RTL design of digital baseband modem 2. lab verification of phy algorithm such as FFT, Viterbi, etc. 3. area/power/
customers using Synopsys Verification tools. Must possess in-depth knowledge of RTL low power design, verification and power
1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 熟悉 FPGA: >> Familiar with Verilog RTL design. >> Familiar with RTL simulation, timing
開發和相關測試 具備條件: - 具3年以上Digital IC design或FPGA開發相關經驗 - 熟悉RTL coding、simulation & synthesis流程及其開發工具使用 - 具C/C++ coding 和 debug 能
our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced
Computer Science. Skills/Experience 2.Good team player and communication skills. 3.Good Knowledge of RTL coding , Chip
1. 負責系統晶片RTL整合,協助晶片bring-up,除錯與特性分析 2. 協助建立FPGA 3. 與Power團隊合作power分析與收斂 4. 與Physical design團隊合作Timing收斂與達成晶片面積目標 5. 與驗證團隊合作
Team player Advantages Experience with hardware design cycle (especially in RTL simulation/debug) Experience with HDLs:
algorithm for our upcoming WiFi products. Duties include but not limited to micro-architecture definition, RTL
1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務 3.具專案管理能力
for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign
Summary : Artilux are looking for an outstanding engineer who is excited to bring new architectures for advanced ICs, with high quality and exceptional performance. Roles & Responsibilities: • Design, simulate, and verify the design of digital blocks/systems • Familiar with digital IC design back-end flow • Handle and complete assigned projects independently • Skillful communication with cross-functional members, and attending the technical meeting
(1)RTL coding for baseband design (2) FPGA implementation
understanding of Design for Testing including Scan/ATPG/BIST/JTAG -Familiar with Verilog -Experiences with RTL and Simulation.
-About 艾盟仕- 國際品牌的營銷伙伴,給予多國在地品牌總代理(台灣、大陸、越南)銷售管理服務。 包括運動系列專業團隊- 快速成長的年輕團隊,邀你一同攜手開拓。 ★工作地點:面談確認後,依個人的居住地再分配門市 【角色定位/工作場景】 1.介紹及銷售商品/店鋪整潔維護/貨品帳務管理 2.商品諮詢與銷售 3.建立顧客關係與維護 4.店務與商品庫存管理 5.主管交付事項 【專業能力/產業歷練】 >具休閒或運動服飾銷售經驗,若具休閒服飾品牌銷售經驗者更佳。 >活潑外性,喜好與人接觸 >有數字觀念,擅長銷售管理 >對流行服飾趨勢瞭解,成為客戶穿搭諮詢伙伴 >願意挑戰業務數字,為自我帶來獎金報酬
relevant state-of-the-arts 3. Experienced in RTL design, IP integration, FPGA verification, or SW/HW co-simulation 4.Pay