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9/17 IC設計工程師

  • 新竹市
  • 經歷不拘
  • 大學

1. SiC功率元件設計與開發 2. 產品功能測試 3. 產品可靠性測試 4. 有機會至日本公司培訓

月薪80,000元以上 員工20人
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6~10人應徵

9/17 數位設計工程師(合成) / Digital Design Engineer (synthesis)

  • 新竹市
  • 經歷不拘
  • 碩士

## Job Description: ­- Management of the system design architecture for the synthesis and FPGA implementation. ­- Floor-Planning and Placement. ­- Write the digital design constraints. ## Skill: - ­Understand the concept of the digital system design is a plus. ­- Familiar with Git version control. ­- Familiar with SDC/XDC file. - Familiar with TCL scripts. ­- Familiar with the backend development tools.

月薪78,000~140,000元 員工60人
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0~5人應徵

9/17 數位驗證工程師 / Digital Verification Engineer

  • 新竹市
  • 1年以上
  • 碩士

## Job Description: - Write testbench for digital design verification. - Verification of digital system level design. - Cooperate with the DSP team on test patterns. - Plan for peripheral board testing. ## Skill: ­- Familiar with SystemVerilog. ­- Familiar with C++ and Python. ­- Familiar with Git version control.

月薪78,000~140,000元 員工60人
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0~5人應徵

9/17 IC 設計工程師

  • 新北市新店區
  • 3年以上
  • 大學

工作技能:撰寫硬體語言程式、數位晶片產品開發、數位電路分析設計、數位電路驗證、FPGA。 擅長工具:Verilog、C、Python、Perl、TCL、EDA、FPGA、RTL、EDA tool: NC-Verilog、Synopsys DC、STA、FPGA prototyping (Xilinx or Altera)、Verdi、Equivalent check。 熟悉:Generic protocol (I2C, SPI, UART, PDM, …)、AHB、APB、DMA、IP或SoC設計開發流程與驗證環境。 具有FPGA相關經驗與熟悉ARM架構者尤佳。 具有IC規格制定經驗,協助客戶澄清技術與應用問題經驗與能力尤佳。

月薪60,000元以上 員工9人 距捷運大坪林站350公尺
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0~5人應徵

9/17 FPGA工程師

  • 台北市中正區
  • 經歷不拘
  • 大學

VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自動交易系統;同時,交易策略橫跨股票、期貨及衍生性商品,且每日全球交易市值達數百億台幣。 我們以人為本,提供開放且自由的工作環境,讓夥伴可以專注於研究與創新,同時,透明且扁平化的組織架構,讓所有人都可以在組織裡發聲並發揮潛能。 我們的研發團隊是技術導向、喜歡研究與實驗、樂於求新求變及接受挑戰以追求極致完美的研發團隊,將來工作中您會高強度的使用軟硬體開發相關的專業知識,如您有高度熱忱學習,渴望快速成長,歡迎加入! 【職務內容】 1. 超高速介面設計 2. 數位模擬 3. AI硬體實現 4. 傳輸協定層開發 5. 硬體延遲最佳化 【具備技能】 1.熟悉 SystemVerilog/Verilog之語言特性,具備硬體描述語言與數位設計概念。 2.具備學習新知與研讀規格的能力與毅力。 3.一顆對FPGA有相當熱情的心。

月薪70,000~100,000元 員工60人
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6~10人應徵

9/17 樺晟電機與恩智區塊鏈聯合招聘:比特幣礦機研發及維修相關人員

  • 新北市新店區
  • 1年以上
  • 學歷不拘

熟維修螞蟻,神馬等礦機 晶片或電路版設計 熟ASIC礦機研發流程 ASIC礦機一年以上生產製造經驗 ASIC礦機相關IC設計工程師 符合以上任一條件

月薪50,000~1,000,000元 員工20人 距捷運大坪林站350公尺
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0~5人應徵

9/16 Physical Design Engineer (PD)- 新北市/ 新竹

  • 新竹市
  • 1年以上
  • 學歷不拘

- Block level and sub-block floor-planning - Discuss SRAM placement with PD team during block level floor-planning stage - Placement optimization for timing and resolve congestion - Clock tree synthesis and clock tree optimization for timing - Routing and routing optimization for post-route timing and resolving congestion - Clean-up DRC error - Post-route timing ECO - Metal ECO - Clean post-route timing violations - Generate SPEF files - English knowledge

月薪55,000~65,000元 員工20人
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0~5人應徵

9/14 [2022 研發替代役] 數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)

  • 新竹市
  • 經歷不拘
  • 碩士

## Job Description: The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes. ## Skill: - Familiar with Verilog RTL implementation from a matlab, python or c algiorithm. - Familiar with RTL simulation, timing analysis. - Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. - Familiar with Xilinx FPGA serdes IO, and selectIO. - Familiar with Xilinx IP design and packaging. - Familiar with at least one FPGA device. - Familiar with Custom IP and SoC integration is a plus.

月薪78,000~140,000元 員工60人
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0~5人應徵

9/14 數位晶片設計工程師(前端) / Digital IC Design Engineer (Frontend)

  • 新竹市
  • 經歷不拘
  • 碩士

## Job Description: The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed serdes. ## Skill: - Familiar with Verilog RTL implementation from a matlab, python or c algiorithm. - Familiar with RTL simulation, timing analysis. - Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. - Familiar with Xilinx FPGA serdes IO, and selectIO. - Familiar with Xilinx IP design and packaging. - Familiar with at least one FPGA device. - Familiar with Custom IP and SoC integration is a plus.

月薪78,000~140,000元 員工60人
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6~10人應徵

9/10 Digital IC design Sr. Engineer 數位IC設計資深工程師

  • 桃園市桃園區
  • 3年以上
  • 大學

Participate on projects involved in development of ASIC with digital circuit design for sensor product. Work closely with LOB RD to optimize performance until product release. 此職務負責感測IC前端數位訊號處理電路設計,將協助產品RD驗證與調教功能直到產品量產 一、 任職資格: 1. 學歷要求:Bachelor’s or Master’s degree in Electronics/Computer sciences/Engineering equivalent。 電子/電機/資工或理工相關系所大學或碩士以上學歷。 2. 年資要求:At least 3+ years of working experiences in IC design / Semiconductor field. 3年以上IC設計開發或半導體晶片開發相關經驗 3. 專業技能要求: Minimum qualifications: 1. Algorithm development,RTL synthesis and verification in sensor field. 相關於感測元件演算法設計開發、RTL整合與驗證。 2. Familiar with EDA design S/W(Debussy/NC-VERILOG/CANDENCE COMFORMAL…) 熟悉EDA設計工具(Debussy/NC-VERILOG/CANDENCE COMFORMAL…) 3. Familiar in sensor(Optical experience is plus) ASIC design verification flow, logic synthesis and integration. 熟悉感測元件ASIC/SoC設計開發與驗證流程與邏輯整合(具光學感測設計經驗尤佳)。 4. Good in designing ADC circuit, sigma-delta process and verification. 具ADC電路設計,Sigma-Delta電路設計與驗證經驗。 5. Familiar in co-work with 3rd party design service company / wafer foundry and related outsourcing resources. 能獨立對接外部設計公司與投片生產單位 6. Fluent in English (minimum TOEIC 500+) both of verbal and written 英語程度多益至少500分 二、 工作職掌: This role will be responsible for: 1. SoC front-end circuit design, simulation and integration. Developing test plan as well as guiding the functional verification. SoC前端電路設計、模擬與整合。開發測試計畫並完成功能驗證。 2. Manage activities, resources, schedule, budgets and ensure cross companies communication to 3rd parties design service. 需與外部設計服務公司合作開發電路設計並管理開發進度 3. You will work closely with LOB product RD for functional verification. 此職務將會與產品工程師合作驗證設計電路功能。 4. This role will be stationed in Taiwan, you need to report working progress routinely to team manager. 工作地點在台灣,向部門主管定期匯報工作進度。 5. You will need to travel abroad to work with production test, application issue solving in case of necessary. 必要時須配合客戶驗證,生產測試驗證等緊急任務需求出差海外

月薪125,000元以上 員工400人
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0~5人應徵

9/09 數位IC設計驗證工程師

  • 台北市松山區
  • 經歷不拘
  • 大學

碩士應屆畢業生 或 大學以上兩年IC設計驗證工作經驗 1.英文溝通無礙:與外國同事合作,需要流利聽讀說能力 2.工作時間彈性:無硬性上班時間,主要配合美國總部開會時間. 3. 無經驗者必需具備數位IC設計相關之論文或專題 4. 熟悉 Verilog, System Verilog 或 UVM. 4. 具有MOS level之基礎知識 5. 個性活潑主動:公司風氣鼓勵積極主動與同事互動討論,且能獨立解決問題 Job Description Summary Maxim’s Micros, Security, & Software Business Unit is seeking an Entry-Level IC Design Engineer in Dallas, Texas to define, design, model, and implement analog, mixed-signal, and/or digital integrated circuits (ICs). As an IC Design Engineer, you will have the opportunity to work on technology for products in exciting industries such as automotive, mobile, cloud & data, industrial, healthcare, and micros & security. Responsibilities and Duties include but not limited to: Design activities including research, definition, design, simulation, layout verification, characterization, and release to production of integrated circuits Supporting product definition teams to develop product requirements and specifications Analyzing and developing chip architectures to meet required compliance and performance Authoring system architecture and circuit documentation Perform RTL design of block level modules Simulate at the block level and SoC level to guarantee design objective specification functionality and timing Simulate and debug gate level timing simulations at SoC level Defining system and block level test plans Characterizing and validating circuit performance in the lab Providing support for high volume manufacturing, and working with Product and Test teams to transfer ICs to production Minimum Qualifications: Pursuing a Bachelor’s degree in Electrical Engineering or related field Solid knowledge of analog and mixed-signal IC design fundamentals Verilog, System Verilog, RTL, Digital Design Preferred Qualifications: Pursing a Master’s Degree in Electrical Engineering or related field Write reusable RTL code, follow design and DFT guidelines Run digital simulations using industry standard tools Write C and Assembly code-based tests to verify SoC functionality Strong background in processor design preferred Have familiarity with System Verilog for verification, OVM/UVM, assertions, cover points Exposure to physical design and timing closure Hands-on IC design experience Superior analytical and problem solving skills

月薪80,000~120,000元 外商公司
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6~10人應徵

9/06 FPGA/軟韌體工程師

  • 新北市汐止區
  • 經歷不拘
  • 大學

具備 Verilog coding 能力 (熟 Lattice FPGA 為佳) 能與硬體 Co-work,對電子電路有基本概念。

月薪50,000~80,000元 員工180人
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0~5人應徵

9/02 Frontend Engineer

  • 新竹縣竹北市
  • 3年以上
  • 大學

(1) Timing Closure Fixing (2) DFT expert (SCAN/ATPG/ MBIST/BSCAN/MBISR/At-Speed) (3) Hierarchical Experience is preferred for 100M+ gate count (4) CAD tool evaluation and consultant for frontend implementation

月薪50,000元以上 員工60人
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0~5人應徵

7/22 資深 IC layout 佈局工程師

  • 新竹縣竹北市
  • 4年以上
  • 專科

1. 具有芯片佈局設計IC Layout 的經驗: 4~8年, 數位, 類比, Mixed mode。 2. 熟悉使用佈局設計工具Layout Tool的運用與學習(Virtuoso , Laker, calibre...)。 3. 可接受進駐新竹科學園區, 台元科技園區的客戶端服務。

月薪52,000~100,000元 員工30人
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0~5人應徵

7/10 IC 驗證

  • 新竹市
  • 經歷不拘
  • 大學

責任 1. 同設計團隊和軟體團隊一起確保晶片功能全面得到驗證; 2. 參與驗證架構的開發; 3. 模組及介面功能建模; 4. 指定並完成驗證計畫; 技能要求 1. 有1年以上複雜晶片/FPGA模組層級或晶片級驗證經驗(各種技術等級) ; 2. 精通SV/C++/Pythen/Perl; 3. 熟悉UVM驗證方法學; 4. 有代碼覆蓋率檢查、形式驗證工作經驗; 5. 有網路晶片驗證經驗者優先; 6. 有以下IP驗證經驗者優先: SerDes, PCIE, CPU Subsystem, Ethernet; 7. 責任心強,善於自我激勵和樂於助人; 8. 易於溝通,具有團隊合作精神; 9. 碩士或本科學歷;

月薪100,000~300,000元 員工50人
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0~5人應徵

7/10 ASIC Design Lead (pp design)

  • 新竹市
  • 7年以上
  • 大學

ASIC Design Lead Responsibilities 1. Design high performance and high-quality ASIC modules from specification to RTL implementation 2. Lead team and responsible for module level spec creation, RTL coding, Lint/CDC check, synthesis, formal check, and timing closure. 3. Co-work with Modeling Team to delivery architecture spec 4. Co-work with Verification team/SW team to validate the chip design. 5. Participate in lab bring up and validation, debug and support Skill requirement 1. 10+ years of experience in Networking ASIC digital design or architecture. 2. Hands-on experience on Verilog HDL coding, able to implement IP/Modules from scratch. 3. Experience on Team management or leadership. 4. Experience on Ethernet Networking Protocols, such as IPv4/IPv6, VXLAN Tunnel. 5. Familiar with Forwarding/Learning concepts and implementation. 6. Knowledge of System Verilog and UVM verification is a plus 7. Good at Unix/Perl/Python scripting is a plus. 8. Highly motivated, positive, detail oriented and responsible. 9. Good team player and good communication skills.

月薪120,000~210,000元 員工50人
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0~5人應徵

5/07 資深類比IC設計工程師

  • 香港特別行政區
  • 3年以上
  • 學歷不拘

工作職責 1. 負責根據晶片規格定義晶片系統架構* 2. 負責根據晶片系統架構定義類比電路系統*及模組的規格定義 3. 負責類比電路設計及類比電路的版圖指導 4. 參與晶片頂層的Floor Plan*以及模組電路的Floor Plan 5. 參與測試計畫的制訂 6. 參與晶片及模組的實驗室測試和標定 7. 負責相應產品及模組的問題分析及Debug 8. 編寫相關中英文設計文檔 職位要求 1. 模擬積體電路的基礎理論。具備量產經驗者優先 2. 精通Cadence EDA工具及其他常規EDA工具 3. 精通VerilogA 或者VHDL等 4. 精通Matlab等系統設計工具 5. 熟悉CMOS工藝流程,熟悉感測器工藝流程者優先 6. 具備感測器讀出電路(IMU或磁感測器)設計經驗者優先 7. 具備低功耗模擬濾波器,低功耗ADC,PLL等設計流片經驗者優先 Position: Senior* Analog IC Design Engineer Responsibilities: 1. Develop system architecture definition* 2. Define system specifications* and building blocks specifications 3. Design analog circuits schematic, and supervise analog / mixed signal circuit layout 4. Floor plan for chip top* and block level 5. Draft test plan for chip and/or building blocks 6. Chip and/or building block test and characterization 7. Product failure analysis and Debug 8. Design documentation Requirement: 1. Be good at theory of analog and/or mixed signal circuit design. Mass production experience preferred 2. Be good at Cadence EDA tools, and other regular EDA tools 3. Be good at VerilogA and/or VHDL 4. Be good at Matlab 5. Familiar with CMOS process. Experience at sensor process (MEMS / AMR) preferred 6. Experience at advanced analog and mixed signal design for sensor readout circuit (IMU or Magnetic Sensor) preferred 7. Experience at low power analog filter, low power ADC, PLL preferred

月薪110,000~130,000元 員工250人
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0~5人應徵

3/11 CPU Technical Lead(Design Engineering Director/Senior Manager)

  • 新竹市
  • 經歷不拘
  • 大學

Introduction We are looking for an outstanding engineer with strong leadership skills to lead the CPU technical development. The successful candidate will be a passionate individual who has significant experience in technical leadership. To be successful in this role, the individual requires strong technical skills, proven track record in specifying and delivering products to market, and proven experience in the technical leadership of highly performing engineering teams. Job Purpose We are looking for an individual with a proven ability to lead and inspire a talented team of hardware engineers, working with engineering management, customers and product management to deliver our industry-leading hardware products. The successful candidate will be responsible for the technical specification of the product, the technical management of the design and validation engineers working on the project, the creation and scrutiny of design and verification specifications, and for driving the team to ensure delivery to specification, quality and schedule. Job requirements Essential Skills and Experience Significant experience of RTL design for complex ASIC products Strong hardware development experience, spanning specification, design, verification, implementation, and delivery. Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product Experience in all stages of the design cycle: initial concept, specification, implementation and testing, documentation and support Experience producing specifications and documentation describing complex designs Ability to work under time-scale pressure and meet aggressive targets without compromising on quality Understanding of the fundamentals of computer architecture Experience in leading a team of highly skilled engineers Excellent communication skills at technical, senior management, and customer levels Highly proactive, with strong multi-tasking skills Strong planning skills Proficiency in problem solving Practical, organised, and analytical approach to work Excellent communication and networking skills Enthusiasm, drive and the ability to schedule own workload and plan tasks Significant technical team leadership experience, including planning, managing tasks and driving delivery to specification and schedule Experience of mentoring and coaching Experience of technical interaction with customers Highly proficient in spoken and written English Desirable Skills and Experience · Practical experience of working on microprocessor designs · Proficiency in scripting languages, e.g. Perl/TCL/Python · Knowledge of assembly language (preferably Arm), C/C++ and/or hardware verification languages e.g. SystemVerilog, Specman ‘e’ · Line management experience · Experience working and communicating with cross-site teams · Understanding of functional safety principles and experience of designer functional safety features

月薪250,000元以上
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0~5人應徵
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