• 全部
  • 全職
  • 兼職
  • 高階
    • 派遣

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1/18 DFT Engineer (MBIST/Scan)

  • 台南市中西區
  • 3年以上
  • 大學

<依學經歷核定職稱> DFT Technical Manager ※Job Contents: 1.工作地點:台南 2.Communicate with customers to provide suitable test architecture planning for production. 3.Communicate with external teams to keep track of issues and progress. 4.Managing schedules and supporting cross-functional engineering effort. 5.Assist DFT structure implementation and review team members' work. 6.Working with test engineers to bring up test vectors on test-house/silicon. DFT Design Engineer - MBIST / SCAN ※Job Contents: 1. DFT Planning of MBIST/SCAN for whole chip. 2. Implement of MBIST and SCAN 3. Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check 4. Discuss with Test Engineers to provide solutions to DFT testing ※Requirements: 1. Graduated in EE or related Engineering 2. Proficient in programming skill and UNIX shell. 3. Compression / Share code / Ultra flow implementation 4. Familiar with Verilog / RTL / STA / Simulation verification flow 5. MBIST/SCAN pattern build up in ATE

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0~5人應徵

1/18 DFT EDA Engineer

  • 新竹市
  • 經歷不拘
  • 大學

※Job Contents: 1. Responsible for IC DFT design methodology development and project support. 2. Flow development for Memory BIST, Scan, Boundary Scan, ATPG and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in DFT flow development (Memory BIST/BISR, SCAN, Boundary Scan, ATPG, Logic BIST, etc) 3. Experience in low power flow development (UPF/CPF/low power check/PSO/DVFS, etc) 4. Post-silicon ATE debug/support experience 5. Proficient in Unix shell/Tcl/Perl and programming skills 6. Proficient in C/C++ and QT 7. 16nm/7nm IC design experiences is a plus

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0~5人應徵

1/18 Test Hardware Development Engineer

  • 新竹市
  • 10年以上
  • 大學

※Job contents 1. Test program development and debugging 2. Test hardware (Probe card, load board, socket) design and verify 3. Project management 4. Test data analysis 5. Collect characterization datalog for process improvement and develop reliability qualification test ※Qualification 1. 10+ years experience with load board/probe card development. Especially for high speed/power product. 2. Familiar with layout, SI/PI/thermal simulation. 3. Good at simulation data analysis and layout improvement 4. Aggressive working attitude 5. Capable to handle new challenge 6. Good communication skill

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6~10人應徵

1/18 Execution Project Manager / General Solution Architect (竹科)

  • 新竹市
  • 10年以上
  • 大學

※Job Contents: 1. 工作地點:Hsinchu 2. Responsible for ASIC tech activities of pre-sale projects, including tech capability promotion, Effective communication with clients for tech and business needs, tech proposal delivery and SOW drafting. 3. Handle ASIC program management and key issue resolving from Netlist-in to Mass production. 4. Business travel is expected. ※Requirements: 1. 10-15 years experience with Chip-level RTL integration leader or SoC chip Implementation Project lead. 2. Good communication and program management skill 3. Familiar with ASIC design flow and product life activities. 4. Familiar with TSMC process (ex. 16nm/7nm), high-speed interface IP, and advanced package and co-sim. 5. System knowledge (ex. Networking or High performance computing) is a plus.

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6~10人應徵

1/18 2.5D/3D-IC Physical Design Engineer

  • 新竹市
  • 經歷不拘
  • 大學

※Job Contents: 1. Develop 2.5D/3D-IC multi-die stacking design flow for TSMC CoWoS, InFO, SoIC advanced technology 2. Deploy and enhance 2.5D/3D-IC physical design flow in real design with performing 3D multi-die stacking tasks: die-stacking configuration, floorplanning, layout, and die-to-die auto-routing 3. Develop 2.5D/3D-IC extraction signoff flow to ensure signal and power integrity 4. Design experience in SoC cell-based APR and verification is required.

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6~10人應徵

1/18 Front-End EDA Engineer

  • 新竹市
  • 經歷不拘
  • 大學

※Job Contents: 1. Responsible for IC frontend design methodology development and project support. 2. Flow development for lint, constraint check, synthesis, STA, power analysis and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in R2N flow development (lint/constraint check/synthesis/STA/Simulation/formal etc) 3. Experience in low power flow development (UPF/CPF/low power check/PSO/DVFS etc) 4. Timing ECO experience 5. Proficient in Unix shell/Tcl/Perl and programming skills 6. Proficient in C/C++ and QT 7. 16nm/7nm IC design experiences is a plus

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0~5人應徵

1/18 Digital SoC IC Design Engineer

  • 新竹市
  • 3年以上
  • 碩士

Job Descriptions: 1.SoC design and verification: Job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, STA and FPGA verification. Job Requirements: 1.MS or PhD degree in EE, CS, or relevant fields 2.Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA 3.Experience in chip integration and familiar with CPU, Bus Fabric, DDR, PCIe and USB is a plus 4.Familiar with Networking application is a plus 5.Familiar with shell scripts for design automation such as Perl language is a plus 6.Fluent in English communication is a plus and need to travel to other country sometimes

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0~5人應徵

1/18 Senior IC design engineer (CPU/DRAM)

  • 新竹市
  • 經歷不拘
  • 碩士

Job Descriptions: 1.Job includes integration of ARM leading edge CPU and world wild tier one DDR4/5 IP. Such as spec study, architecting and performance analysis, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. Job Requirements: 1.MS or PhD degree in EE, CS, or relevant fields 2.Familiar with ARM CPU series such as A7x/A5x/DSU…etc., 3.Familiar with DDR4/3 PHY/Controller integration 4.Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA 5.Familiar with shell scripts for design automation such as Perl language is a plus 6.Fluent in English communication is a plus

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0~5人應徵

1/18 客服助理

  • 新竹市
  • 經歷不拘
  • 專科

1. 秘書業務:部門日常庶務, 訪客接待, 請款, 採購, 年度預算管控,國內外差旅等 2. 會議安排:主管會議安排與會議資料整合 3. 內部專案與部門事務聯絡窗口 4. 部門文件檔案管理 5. 其他主管交辦事項

月薪35,000~55,000元 上市上櫃 員工817人
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30人以上應徵

1/18 Analog CAD Engineer

  • 新竹市
  • 3年以上
  • 大學

※Job Contents: 1. IP design flow development 2. In-house utility development for IP design 3. EDA tool evaluation, usage, maintenance, Q&A window with tool vendor 4. 具備programming 能力 ( C/C++, TCL script, C-shell 或perl 其中一項以上 ) 5. Familiar with Virtuoso SKILL writing, Calibre rule writing, or other EDA tools is a plus. ※Requirements: 1. 熟 Verilog language, Verilog simulator 2. 有IP behavioral model 開發經驗更好 3. 了解.lib model, SDF format 更好 4. 熟悉Memory BIST/BISR/ECC 更好

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0~5人應徵

1/18 Digital IP Design Engineer

  • 新竹市
  • 3年以上
  • 大學

※Requirements: 1. DDR/LPDDR/GDDR/HBM logic design and verification 2. RTL design 3. Digital Design Checks : CDC, LEC, STA, and etc. ※其他條件 1. Over 3-year digital design experiences 2. Familiar with DDR/LPDDR/HBM/SerDes or DSP is plus 3. Familar with digital IC front-end design flow such as Verilog RTL design, Synopsys Design Compiler, LEC, Spygalss, PrimeTime STA

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0~5人應徵

1/18 Design Service Technical Leader

  • 新竹市
  • 10年以上
  • 大學

※依據您的資歷核定職稱。  ※Requirements: 1. 10+ years experiences in ASIC/SOC design and 3+ years in project lead function 2. Fully understand ASIC/SOC flow, stages and milestones 3. Understand Physical design flow including APR, physical/power/low power verification flow.   4. Understand synthesis, SDC and timing closure flow  5. Understand DFT including SCAN, MBIST, and BSD flow.  6. Familiar with hierarchical/low power design 7. Experiences in 40/28nm process project tapeout is a must, 16um and below is a big plus 8. Strong customer oriented mindset and internal resource utilizing skill 9. It's the most challenge work in ASIC/SOC design filed along with tremendous ASIC/SOC knowledge accumulation/application and strong sense of accomplishment. 10. English communication capability is a must. 11. 工作地點:新竹

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0~5人應徵

1/18 Layout Engineer

  • 新竹市
  • 3年以上
  • 專科

※Job Contents: 1.Mix mode 2.Analog layout 3.Full Customer Layout ※Requirements: 1.具類比IP、special I/O、Mixed mode full custom layout經驗。 2.具full custom IC layout / verification經驗。 3.具 Laker/Virtuoso, Calibre LVS / DRC/ Calibre等工具經驗。 4.具16/ 7/5nm IC layout experiences is a plus. 5.歡迎有IC layout經驗3年以上者加入。

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0~5人應徵

1/18 資深數位IC設計工程師

  • 新竹市
  • 3年以上
  • 大學

●工作內容 1. PCIe, Ethernet, and digital signal processing IP design and verification 2. Architecture design, RTL coding, simulation, linting, CDC, synthesis, LEC, STA and FPGA verification ●條件 1. Over 3-year digital design experiences 2. With front-end design flow knowledge, Verilog RTL, linting, synthesis, LEC, STA, and CDC is must 3. Familiar with PCIe, SATA/SAS, Ethernet, USB or digital signal processing logic is plus 4. Experience in chip integration is a plus 5. Familiar with Systemverilog or UVM is plus 6. Familiar with FPGA emulation is a plus

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0~5人應徵

1/18 IP Subsystem Project Manager

  • 新竹市
  • 10年以上
  • 碩士

※Job Contents: 1. Manage outsourcing engineers, Plan and review their works/throughout for the project execution 2. Enhance IP Subsytem Package Deliverables that facilitate SoC and IP Testing Integration 3. 3rd-Party IP Deliverable Quality Check 4. SoC/IP/Sub-system design & technical consult for ASIC design service 5. IP & Sub-system design and technical supporting for customer ASIC projects 6. High-Speed Interface (Ex.USB 2.x/3.X, SerDes-28G/56G/112G, ...etc) IP technical supporting ※Requirements: 1. MS/PhD EE or CS related departments 2. A minimum of 10+ years IC design experience with 3 years project experience preferred 3. Well knowledge on IC design flow (include frontend, backend, DFT, low power design, package design and CP/FT testing) 4. High-Speed IP design experience in one of the following list: DDR, PCIE, USB, SerDes, HDMI and MIPI 5. Excellent communication and interpersonal skills 6. Fluent in English

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0~5人應徵

1/18 Senior IC Design Engineer / Technical Manager

  • 新竹市
  • 4年以上
  • 碩士

Job Descriptions: 1.Lead a subsystem front-end design/verification tasks from RTL to netlist. 2.Subsystem includes AMBA based subsystem or high speed communication subsystem like PCIe. 3.Main job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. Hands-on capability is necessary 4.Use communication and leadership skills to help the team to achieve the goal Job Requirements: 1.MS or PhD degree in EE, CS, or relevant fields 2.Proven industry experience over 8 years 3.Familiar with CPU sub-system design/integration such as CPU, Bus Fabric, DDR, PCIe and USB 4.Good at digital IC front-end design flow such as RTL design, Lint/CDC, Synthesis, LEC/formality, PrimeTime STA 5.Experience of analog IP integration such as PHY, Serdes and PLL 6.Experience of IC backend design flow such as DFT, P&R, post-silicon system level debugging and ATE debugging 7.Experience of leading a task force for more than 3 members to complete the task 8.Familiar with UVM/System Verilog simulation skills is a plus 9.Familiar with shell scripts for design automation such as Perl/Python language is a plus 10.Fluent in English communication

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0~5人應徵

1/19 電子商務業務與行銷主任專員_自有品牌Innergie (台北)

  • 台北市內湖區
  • 8年以上
  • 大學

1. 實體通路和電子商務營銷策略規劃與管理 2. 客戶溝通與管理 3. 通路品牌形象廣告、展櫃布置 4. 大型展覽展會以及支援海外據點與經銷商之展覽佈置與宣傳物 5. 網站維護與管理

待遇面議 上市上櫃 員工83000人
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30人以上應徵

1/18 電子設計資深工程師_電動車充電樁(中壢)

  • 桃園市中壢區
  • 經歷不拘
  • 大學

想知道電子設計工程師的一天嗎? 給我三分鐘,讓你一窺台達EE的一天 影片傳送門在此:: https://www.youtube.com/watch?v=b33Lrotur1w 工作任務:負責電動車無線充電樁系統研發設計 1.

待遇面議 上市上櫃 員工83000人
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11~30人應徵

1/18 電子設計資深工程師_風扇暨熱傳導產品(桃二)

  • 桃園市龜山區
  • 經歷不拘
  • 碩士

想知道電子設計工程師的一天嗎? 給我三分鐘,讓你一窺台達EE的一天 影片傳送門在此: https://www.youtube.com/watch?v=b33Lrotur1w ※工作內容: 1. 電子電路設計; 2. 執行新產品開發可行性評估;

待遇面議 上市上櫃 員工83000人
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6~10人應徵
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