Memory IP Design Engineer
- 新竹市
- 3年以上
- 大學
Applicant will have Test, design and verification responsibilities for Allegro's internally developed custom memories including SRAM, ROM, One-Time-Programmable, and EEPROM. Responsibilities: - Transistor-level circuit design, simulation, and testing. - Create test/validation plan for different sizes of memories. - Documentation/application note development and customer support. Job Requirements: BSEE or MSEE with 2+ years' experience with memory design, circuit simulation and testing; knowledge of transistor level circuit design and layout; knowledge of CMOS fabrication methods and digital circuits; experience with layout parasitic extraction and simulation tools; strong written and verbal communication skills; experience with Unix shell languages; understanding of issues and modeling of variation in deep sub-micron technologies; knowledge of verilog modeling; familiarity with layout verification tools, design rules, and rule decks.