Job description
Are you a passionate verification engineer who loves to work on complex systems, building test environments which find all the bugs before anyone else find them? Do you pay attention to the latest in verification technologies to make sure you're as efficient as possible while working on increasingly complicated IPs? We have fantastic opportunities for experienced and highly motivated verification
engineers to join a fast-growing team and develop our next generation of CPUs.
As an important member of our development team you'll predominantly be involved with employingconstrained-random coverage-driven simulation techniques using SystemVerilog and UVM, both with hands-on project work and leading junior engineers.
Experience
• designing and implementing verification environments for RTL designs.
• fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory
systems
Skill
• Familiar SystemVerilog and verification methodologies (UVM, OVM)
• Scripting languages. (Python or Perl) is a plus.
• Formal Verification testbenches is a plus.
• Software engineering skills (object-oriented programming, data structures, and algorithms)
Additional responsibility for Senior and higher levels:
• design verificationor digital design for comprehensive functional blocks with technologies.
(computing, multimedia, or communication)
Proven delivery record in CPU or similar level of model
• analysis, design, implementation, verification, or validation for program flows, memory flows, I/O flows, asynchronous event flows, compute pipes, as well as system, processor, and pipe controls.
待遇面議