4/23 系統工程師-晶片驗證
- 紘康科技股份有限公司
- IC設計相關業
- 台北市士林區
- 經歷不拘
- 大學
1.MCU晶片電氣特性驗證。 (firmware coding) 2.晶片,IP function debug. 3.電路圖繪製PCB Layout。 4.測試說明書與技術文件撰寫。 5.協助晶片異常分析與處理。
1.MCU晶片電氣特性驗證。 (firmware coding) 2.晶片,IP function debug. 3.電路圖繪製PCB Layout。 4.測試說明書與技術文件撰寫。 5.協助晶片異常分析與處理。
1.協助類比晶片工程師設計進行晶片測試工作。 2.依據工程師規劃的驗證計畫,進行確認晶片電路之訊號測試結果並整理測試資料。 3.需瞭解與使用Scope, BERT, Network Analyzer, Spectrum Analyzer等高階儀器
系:理工科系尤佳 ★期間限定:即日起至113/8/31前接獲宜特任用通知且依約定報到日如期到任者 ★到任獎金:如期到任者享15萬元到任獎金 因為重視,我們做的比你想的多更多! 加入宜特,讓夢想靠岸, 超越顛峰,從現在開始~ 工作內容: 1.晶片
計劃以驗證設計晶片的高速訊號質量 • 低速訊號測量與調試(I2C/SMBus...等) • 總結、分析和報告驗證結果並支援調試
1.Chip level IR drop 分析 2.Chip power estimation/calculation 3.IR drop flow 建構 4.IR drop tool 維護 5.撰寫程式
統整合。 • 使用 Verilog 設計和功能模擬。 • 使用 FPGA 進行功能驗證。 • 晶片合成並完成 DFT,multi-clock 和 timing 等設計。 • 與後段整合合作,完成晶片驗證並T/O。 您需要具備的條件: • 碩士畢業
1. 電聲產品設計研發包含麥克風 / speaker 、熟悉聲學量測設備(Soundcheck, Audio Percision…etc) 2. 聲學系統設計、音頻相關晶片驗證、音頻參數調整及問題分析改善 3. 開發治具協助導入工廠產線並制
成晶片驗證並T/O 【需求條件】 1. 碩士畢業,數位IC設計3年以上經驗 2. 熟悉ASIC設計和開發流程 3. 熟悉Verilog, Synthesis, formal, STA, FPGA驗證等流程 4. 熟悉上層整合和IP介面 5. 具有
尋找具有嵌入式系統開發經驗的人材,從事嵌入式系統FW/SW領域所包含的FW/SW設計開發、芯片驗證、產品化…等相關工作。 具備以下經驗與技能: -- 嵌入式系統FW/SW設計開發 (ARM / RISC-V平台) -- 晶片驗證 (Chip
1. 晶片表面化學修飾及生物修飾與驗證。 2.表面有機物質分析。 3. 獨立設計實驗與建立檢測之方法學。 4. 熟悉實驗室操作流程、實驗數據整理。
1. RTL 電路設計與功能模擬 2. FPGA 驗證 3. Timing closure 4. 晶片驗證與問題分析
工作技能:撰寫硬體語言程式、數位晶片產品開發、數位電路分析設計、數位電路驗證、FPGA。 擅長工具:Verilog、C、Python、Perl、TCL、EDA、FPGA、RTL、EDA tool: NC-Verilog、Synopsys DC、
Provide design verification services for our SoC ※ Responsibilities: • Test bench development using System Verilog UVM • Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections • Regression setup and debug at RTL level and gate sim level working with design team
The Role: As a Design Verification Infra engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and support for DV Infra and tools both for Taiwan and India, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance. Responsibilities Infrastructure Development: - Design, develop, and maintain the verification infrastructure for CPU designs. - Create and enhance testbenches, simulation environments, and automation flows. - Collaborate with design and verification teams to ensure seamless integration of tools and methodologies. Tool Familiarity: - Proficiency in C++, Scala, and Python is essential. - Use these languages to build custom tools, scripts, and utilities for verification tasks. - Familiarity with other EDA (Electronic Design Automation) tools used in verification (such as VCS, Verdi, and SpyGlass) is advantageous. Emulation Platform Support: - Work closely with the emulation platform teams to optimize verification workflows. - Collaborate with cross-functional teams across different geographical locations (Taiwan and India).
尋找具有嵌入式系統開發經驗的人材,從事嵌入式系統FW/SW領域所包含的FW/SW設計開發、芯片驗證、產品化…等相關工作。 具備以下經驗與技能: -- 嵌入式系統FW/SW設計開發 (ARM / RISC-V平台) -- 晶片驗證 (Chip
1. RTL 電路設計與功能模擬 2. FPGA 驗證 3. Timing closure 4. 晶片驗證與問題分析
NEUCHIPS is looking for skilled engineers for virtual prototyping of AI chips. Responsibilities: - Design virtual prototyping and architecture of SoC - Develop SystemC TLM models of AI accelerator - Analyze and optimize AI SoC architectures for performance and power Qualifications/Skills: - Understanding of C++/SystemC/Verilog - Familiarity with scripting (such as TCL, python, or Perl language) - Familiarity with AMBA protocol is a plus - Experience in IC development flow is a plus - Experience in virtual prototyping tools (e.g., Synopsys Platform Architect) is a plus Education and experiment requirements: - MS/Ph.D., Electrical Engineering or Computer Science
Andes Deep Learning Accelerator (AnDLA) is a highly efficient and cost-sensitive AI solution for edge devices and endpoints. AnDLA features hardwired processing units for matrix multiplication, convolution, pooling functions, and more in the future. You will develop functional verification infrastructure and create test patterns to ensure functional correctness of the AnDLA IP. You will develop test plans for various verification environments, such as self-check UVM environment and system-level verification with AndesCore processors. You will be involved in the AnDLA specification and micro-architecture discussion. You will work closely with the design engineers to ensure functional correctness. =================== Responsibilities =================== Verify for AnDLA IP. Build functional verification infrastructure, which includes various verification environments. Produce test plans and test patterns. Check the test coverage.