4/22 類比晶片驗證副工程師
- 苗栗縣竹南鎮
- 經歷不拘
- 大學
1.協助類比晶片工程師設計進行晶片測試工作。 2.依據工程師規劃的驗證計畫,進行確認晶片電路之訊號測試結果並整理測試資料。 3.需瞭解與使用Scope, BERT, Network Analyzer, Spectrum Analyzer等高階儀器
1.協助類比晶片工程師設計進行晶片測試工作。 2.依據工程師規劃的驗證計畫,進行確認晶片電路之訊號測試結果並整理測試資料。 3.需瞭解與使用Scope, BERT, Network Analyzer, Spectrum Analyzer等高階儀器
1.MCU晶片電氣特性驗證。 (firmware coding) 2.晶片,IP function debug. 3.電路圖繪製PCB Layout。 4.測試說明書與技術文件撰寫。 5.協助晶片異常分析與處理。
系:理工科系尤佳 ★期間限定:即日起至113/8/31前接獲宜特任用通知且依約定報到日如期到任者 ★到任獎金:如期到任者享15萬元到任獎金 因為重視,我們做的比你想的多更多! 加入宜特,讓夢想靠岸, 超越顛峰,從現在開始~ 工作內容: 1.晶片
計劃以驗證設計晶片的高速訊號質量 • 低速訊號測量與調試(I2C/SMBus...等) • 總結、分析和報告驗證結果並支援調試
統整合。 • 使用 Verilog 設計和功能模擬。 • 使用 FPGA 進行功能驗證。 • 晶片合成並完成 DFT,multi-clock 和 timing 等設計。 • 與後段整合合作,完成晶片驗證並T/O。 SystemVerilog/C/
1.Chip level IR drop 分析 2.Chip power estimation/calculation 3.IR drop flow 建構 4.IR drop tool 維護 5.撰寫程式
統整合。 • 使用 Verilog 設計和功能模擬。 • 使用 FPGA 進行功能驗證。 • 晶片合成並完成 DFT,multi-clock 和 timing 等設計。 • 與後段整合合作,完成晶片驗證並T/O。 您需要具備的條件: • 碩士畢業
1. RTL 電路設計與功能模擬 2. FPGA 驗證 3. Timing closure 4. 晶片驗證與問題分析
1. 電聲產品設計研發包含麥克風 / speaker 、熟悉聲學量測設備(Soundcheck, Audio Percision…etc) 2. 聲學系統設計、音頻相關晶片驗證、音頻參數調整及問題分析改善 3. 開發治具協助導入工廠產線並制
尋找具有嵌入式系統開發經驗的人材,從事嵌入式系統FW/SW領域所包含的FW/SW設計開發、芯片驗證、產品化…等相關工作。 具備以下經驗與技能: -- 嵌入式系統FW/SW設計開發 (ARM / RISC-V平台) -- 晶片驗證 (Chip
尋找具有嵌入式系統開發經驗的人材,從事嵌入式系統FW/SW領域所包含的FW/SW設計開發、芯片驗證、產品化…等相關工作。 具備以下經驗與技能: -- 嵌入式系統FW/SW設計開發 (ARM / RISC-V平台) -- 晶片驗證 (Chip
工作技能:撰寫硬體語言程式、數位晶片產品開發、數位電路分析設計、數位電路驗證、FPGA。 擅長工具:Verilog、C、Python、Perl、TCL、EDA、FPGA、RTL、EDA tool: NC-Verilog、Synopsys DC、
成晶片驗證並T/O 【需求條件】 1. 碩士畢業,數位IC設計3年以上經驗 2. 熟悉ASIC設計和開發流程 3. 熟悉Verilog, Synthesis, formal, STA, FPGA驗證等流程 4. 熟悉上層整合和IP介面 5. 具有
1. 晶片表面化學修飾及生物修飾與驗證。 2.表面有機物質分析。 3. 獨立設計實驗與建立檢測之方法學。 4. 熟悉實驗室操作流程、實驗數據整理。
1. RTL 電路設計與功能模擬 2. FPGA 驗證 3. Timing closure 4. 晶片驗證與問題分析
1. Embedded ARM CortexM系列 SOC 實作。 2. AMBA platform architecture design. 3. Constraint scripting for synthesis 4. Equivalency checking 5. UPF scripting 6. Power simulation
Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!
和驗證