5/22 企業差旅規劃管理師
- 智原科技股份有限公司
- 半導體製造業
- 新竹市
- 3年以上
- 大學
1. 差旅機票、國內外住宿及交通安排 2. 查詢、辦理各國護照及簽證 3. 差旅期間突發情況應變處理&回報 4.差旅報表彙整及分析 5. 國內外貴賓接待規劃與安排 6. 新竹區油費補助調查
1. 差旅機票、國內外住宿及交通安排 2. 查詢、辦理各國護照及簽證 3. 差旅期間突發情況應變處理&回報 4.差旅報表彙整及分析 5. 國內外貴賓接待規劃與安排 6. 新竹區油費補助調查
本職缺主要工作內容為I/O電路設計, 從較低速一般應用的GPIO, 到較高速特定介面應用的I/O (ex: SD, eMMC, ONFi, DDR, …etc.) 均有機會接觸與開發。針對計畫需求亦會開發客製化I/O以因應各式特殊需求。因I/O與ESD/Latch-up息息相關,亦會學習設計並review ASIC ESD floorplan。此外,開發的DDR I/O 會被公司內的DDR-PHY IP使用,未來若有興趣,可選擇繼續往DDR-PHY高速介面發展,抑或協助設計DDR-PHY中所需要的Analog block。
1.負責 Internet & Intranet 網路維護及問題排除 1.1. Switch, Router 1.2. MPLS & IPsec VPN 2.管理及維護網路監控系統及撰寫script 自動化管理 3. 分析及解決 User & Server 各端點網路問題檢測及分析各種網路安全,防制網路駭客入侵及提出防護作法
1. 機密資訊保護專案規劃及執行 2. 文件管理流程及系統維護、管理及優化 3. 品質系統文件建立、發行、管理及維護 4. 內/外部文件管理及維護 5. 執行文件管理專案及報表分析 6. 配合公司內外部品質稽核及認證作業
1. Business development to explore biz opportunity, key success factors and IP/solution planning for the target applications. (e.g., data networking, display, AIoT, IIoT …) 2. Responsible for pitch book, promotion material and value selling. 3. Business intelligence, strategy and competitive analysis about process technology, design service and target applications. 4. Market survey to identify the biz opportunity of emerging applications. 5. Collaboration with 3rd party and partners to create biz synergy.
1. 人力資源行政作業執行與優化 2. 人才發展與績效管理作業推動 3. 跨部門專案規劃執行及成效追蹤 4. 全球人力資源政策規劃與專案推動 5. 人力資源管理指標建立及數據分析 6. 公司年度策略會議統籌規劃與執行 7. ESG專案事項執行與追蹤
1. 具環境安全(衛生)管理師證照、負責環安衛管理系統規劃、執行與成效檢核追蹤 2. 溫室氣體盤查與查證、碳管理及ESG報告書相關章節撰寫 3. 規劃並推動公司ESG策略、管理、問題追蹤及解決方案 4. 收集、分析國內外永續趨勢及訂定執行策略與短、中、長期目標 5. 其他
1.Familiar with market trend in broadband related field. 2.Cost evaluation, feasibility study, specs discussion with customers and coordinating with RDs. 3.Coordinate related project stuff with cross function team to insure SOC move to mass production smoothly.
1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
1. Product planning, including market survey, positioning and customer engament, for IP and application. 2. Strategic analysis for process & IP development, potential customers and applications. 3. Lead cross functional teams to architect solutions for new market and applications.
1. Implement memory compiler design utilities. 2. Develop memory IP design flow. 3. Familiar with C/C++, Tcl, and c shell. 4. Familiar with memory design, it’s plus 5. Familiar with liberty, verilog, tessent or DFT models, it’s plus
1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
從前段測試可測性至量產 1.Test review 2.IP test 3.ASIC test 4.Low yield分析
1.可獨立作業並執行資訊相關業務(資訊安全作業查核、資訊設備報修維護與規劃、異地備份執行與管理) 2.能執行資安相關稽核作業,整合與查核 IT infra 系統相關參數是否符合資安規範 3.蒐集國內外資安新聞、知識 4.黃區維護作業(列管系統/特權密碼管理) 5.資安內外部稽核規劃與執行 6.熟ISO 27001資訊安全管理系統尤佳
1. Functional IP Selling and technical Presale 2. Maintain Key customer and create potential customers 3. Good communication and negotiation in English.
1) SAR/ Pipline ADC design 2) Current /R2R DAC design
1.Chip level IR drop 分析 2.Chip power estimation/calculation 3.IR drop flow 建構 4.IR drop tool 維護 5.撰寫程式
General OSC/PLL/DLL/SSCG/CDR design & production experience 1) LC-tank VCO design & production experience 2) CDR design & production experience
1. 總機諮詢、電話接聽服務 2. 來賓、客戶接待服務 3. 公文、郵件收發服務 4. 文具訂購服務 5. 其他庶務及主管交辦事項