台灣三星電子股份有限公司

-Objective, mission a. Experiences in PMIC IC IP design and integration b. Executes the rigorous/completeness technical specification c. Co-work with headquarter design and testing engineers to complete chip design/testing/debug for mass production -Main responsibilities High performance Buck converter (COT/CM/VM), Switch design or Low IQ/High PSRR LDO, simulation and integration. -Daily works Co-work with colleagues to define the circuit architecture and execute the plan for design/debug the advanced IP Work smart and work hard to make sure the design quality and schedule Communicate with headquarter for the product developing

- In charge of Memory biz. development & sales for customer application - Responsible for agent management (Inventory mgmt, biz process mgmt.etc). - SCM management (Sales Capability, Forecast Accuracy, Month-End Sales). - Communication with HQ & gaining necessary support for biz strategy implementation. - Daily customer relationship optimization & maintenance. - Market sensing & information collection for biz. analysis.

SOC-PI team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GDS: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow except DFT and P&R Join us, you will work together with expertise in all these areas; you will not only work for physical implementation, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Netlist generation and STA analysis - Synthesis, Netlist quality check, Formal Verification and constraints creation and validation, timing budget. - Co-work with PD engineers to implement chip partition and floorplan - Work in conjunction with RTL designer and PD engineers to achieve timing closure for both partition and full chip level - Achieve special timing closure, such as io, test, clock etc. - Flow automation development, Methodology in any of above areas. What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC/PT/Formality), Cadence (LEC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

[ Information Security Function ] 40% 1. 資訊安全政策推展與規劃 2. 內部系統資安漏洞缺失檢核、防範措施規劃 3. 防火墙設定與管理 4. 其他支援事宜：資安報告產出 [ Access control Function ] 30% 1. CCTV監控、門禁和警報系統等門禁功能相關系統維運負責，並及時應對任何安全事故或違規行為。 2. 管理和領導保全團隊，監督和培訓安保人員並分配工作。 [ Fire Safety Management ] 20% 1. 策劃並組織保全人員/員工的消防演習和培訓，以確保他們的安全。 2. 與當地消防局和監管機構溝通，確保遵守消防安全法規。 [ Others ] 10% 1. 內部系統異常排除 2. 安全風險專案 (如安防設備採購、導入) 3. 其他主管臨時交辦事項

Product : OLED DDI 1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of IC design flow. 5. Scripting experience using scripting languages like Perl and Python.

1. Design and develop image processing IP for OLED panel application 2. Work with algorithm team to implement RTL design 3. Familiar with RTL design and verification 4. Have experience of display driver IC or display TCON IC

SOC-PD team is hiring both junior and senior engineers, whose work scope is physical design from netlist to GDS: P&R, design quality check, partitioning, timing analysis/fixing/signoff, DRC, LVS, IR, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical design, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - P&R implementation - Floorplan, Powerplan, Place, CTS, Routing, Physical Verification and IR drop analysis - Co-work with PI engineers to implement chip partition and floorplan - Work in conjunction with PI engineers to achieve timing closure for both partition and full chip level - Flow automation development, Methodology in any of above areas. What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in digital design, physical design - Hand-on experience in EDA software from Synopsys (ICC2/FC/ICV), Cadence (Innovus), Ansys(RH/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

- Achieve monthly & yearly sales goal - Manage sales related work (PO, A/R, Inventory) - Daily Communicate between customers and HQ - Collaborate with marketing team for market sensing - Manage Samsung SCM and successfully achieve KPIs - Communicate/system-operations between customers and HQ [Others] - Strong network in Taiwan panel industry would be plus(Monitor/TV). - Good command in English speaking and writing. - Familiar with Microsoft Word, Excel and PPT. - Customer focus, external network, aggressive, outgoing, active and good teamwork spirit.

1. [Market analysis] To identify and track the technology industry trend and market sensing regarding to technology, competitors and end market demand. In-depth understanding for tech sector, particular in foundry, advanced packaging and AI. 2. [Business opportunity identification] Perform in-house solution response scenarios projections (business modeling), TAM(Total Addressable Market) analysis, and identification of actual BO(Business Opportunity) including proposal execution and requirements draw-up. 3. [Customer management] Select potential customers and partners and build and manage networks with them. 4. [Target management] Review the possible scenarios for each stage and manage targets to turn them into actuals.

【Main responsibilities】 1. Support technical discussion in promotion stage based on the knowledge of process and IP roadmap. 2. Provide design guidance based on SF design methodology, and support technical QnA for design issues. 3. Support technical discussion for process related QnA and issues resolving after tapeout. 4. Communicate for technical QnA and issue resolving between customer and HQ 【Objective, Mission】 1. Understanding SF process and IP roadmap for technical support in promotion stage 2. Understanding SF chip design flow and design methodology for customer design support 3. Understanding HQ technical team's role and communication channel