台灣三星電子股份有限公司

SOC-PI team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GDS: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow except DFT and P&R Join us, you will work together with expertise in all these areas; you will not only work for physical implementation, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Netlist generation and STA analysis - Synthesis, Netlist quality check, Formal Verification and constraints creation and validation, timing budget. - Co-work with PD engineers to implement chip partition and floorplan - Work in conjunction with RTL designer and PD engineers to achieve timing closure for both partition and full chip level - Achieve special timing closure, such as io, test, clock etc. - Flow automation development, Methodology in any of above areas. What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC/PT/Formality), Cadence (LEC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

Product : OLED DDI 1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of IC design flow. 5. Scripting experience using scripting languages like Perl and Python.

SOC-PD team is hiring both junior and senior engineers, whose work scope is physical design from netlist to GDS: P&R, design quality check, partitioning, timing analysis/fixing/signoff, DRC, LVS, IR, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical design, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - P&R implementation - Floorplan, Powerplan, Place, CTS, Routing, Physical Verification and IR drop analysis - Co-work with PI engineers to implement chip partition and floorplan - Work in conjunction with PI engineers to achieve timing closure for both partition and full chip level - Flow automation development, Methodology in any of above areas. What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in digital design, physical design - Hand-on experience in EDA software from Synopsys (ICC2/FC/ICV), Cadence (Innovus), Ansys(RH/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

1. [Market analysis] To identify and track the technology industry trend and market sensing regarding to technology, competitors and end market demand. In-depth understanding for tech sector, particular in foundry, advanced packaging and AI. 2. [Business opportunity identification] Perform in-house solution response scenarios projections (business modeling), TAM(Total Addressable Market) analysis, and identification of actual BO(Business Opportunity) including proposal execution and requirements draw-up. 3. [Customer management] Select potential customers and partners and build and manage networks with them. 4. [Target management] Review the possible scenarios for each stage and manage targets to turn them into actuals.

[Main responsibility] - Communication between Taiwan branch and Korea HQ and then ensure all CO activities could be done correctly in time. [Daily works] - Writing HQ's report in korean. - Communication between Taiwan branch and Korea HQ. - Prepare Forecast(SOK-BO) and Month-End activities. [Mission] - Make sure and manager all works of Finance part are fully compliant with HQ's guideline and policy. - Know how to control business risk and solve issues efficiently. - Ensure the whole works are correctly and smoothly done in time. - Understand Samsung's vision, strategy, mission and then set goals for Finance part.

SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS. Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc - PPA optimization What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality), Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

-Objective, mission a. Familiar with analog circuit design and Mass production experience, like Bandgap reference, OPAMP, Receiver, DAC, ADC, Level shifter, … etc.. b. LCD driver circuit design experience is a plus. -Main responsibilities Display Driver IC Analog Block Design and Whole Chip Handling for TV Panel -Daily works Co-work with colleagues to design a DDI chip. On-time deliver for requested jobs is must.Communicate with HQ and related development departments for high quality product. -Customer LCD Module Maker