台灣英飛朗股份有限公司

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Job Description The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the design and implementation of the high-speed, highperformance analog / mixed-signal verifications, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high-speed transmission. Essential Functions and Key Responsibilities: • Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance. • Perform the functional verification and timing analysis on the IPs and the blocks. • Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity. • Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. Mandatory Knowledge/Skills/Abilities: • Has intimate knowledge of UVM verification flow. • Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems. • Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++. • Have a decent understanding in CMOS analog / mixed signal design. Preferred Knowledge/Skill/Abilities: • Able to create IBIS-AMI model. • Can code in System-Verilog (WREAL). • Fluent in verbal and written communications. • Independently resolves issues and conquer design challenges. • Self-motivated and detail oriented. • Has good interpersonal skills. Education and Experience Requirements: • M.S. in E.E. with 8+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience Additional Job Description: Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Essential Functions and Key Responsibilities: • Work close with circuit designers to optimize the floor plan; • Perform daily layout editing, DRC/LVS tasks to ensure the quality of the layout; • Create a solid power grid for better power integrity; • Work with the circuit designers to optimize the quality of the layout, including but not limited to matching and signal integrity; • Employ efficient design methodologies to reduce the number of iterations and to deliver the product promptly. Mandatory Knowledge/Skills/Abilities: • Extremely familiar with layout editing tools, such as Virtuoso; • Highly proficient with DRC/LVS/ERC related tools and flows, such as Calibre, PVS (or IC Validator); • Have extensive experience designing layout in deep sub-micron CMOS technologies, especially FinFET technologies (7nm and 5nm); • Decent understanding in the issues of electro-migration and IR drop, RC delay, self-heating, capacitive cross-talk, etc.; • Decent understanding in analog layout requirements, such as matching and shielding; • Knowledge in automatic P&R or chip-level floor planning and chip-level layout integration. Preferred Knowledge/Skill/Abilities: • Decent Understanding in analog design methodologies, including the use of layout constraints; • Knowledge in performing RC extraction and EM/IR analysis; • Knowledge in CAD tool setup and maintenance; • Ability to generate pCell and pyCell to facilitate layout design; • Excellent communication skills and team spirit to work with members across multiple sites and functionalities; • Experience in designing layout for high-speed, high-performance analog, and mixed-signal circuits. Education and Experience Requirements: • BS degree or equivalent; • Have more than 10 years' experience in analog and mixed signal layout design. Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.