Principal Engineer, AMS Verification

08/20更新
3 天內處理過履歷
應徵

工作內容

Job Description The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the design and implementation of the high-speed, highperformance analog / mixed-signal verifications, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high-speed transmission. Essential Functions and Key Responsibilities: • Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance. • Perform the functional verification and timing analysis on the IPs and the blocks. • Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity. • Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. Mandatory Knowledge/Skills/Abilities: • Has intimate knowledge of UVM verification flow. • Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems. • Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++. • Have a decent understanding in CMOS analog / mixed signal design. Preferred Knowledge/Skill/Abilities: • Able to create IBIS-AMI model. • Can code in System-Verilog (WREAL). • Fluent in verbal and written communications. • Independently resolves issues and conquer design challenges. • Self-motivated and detail oriented. • Has good interpersonal skills. Education and Experience Requirements: • M.S. in E.E. with 8+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience Additional Job Description: Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

工作待遇

待遇面議

(經常性薪資達 4 萬元或以上)

工作性質

全職

上班地點

新竹縣竹北市高鐵東二路

管理責任

不需負擔管理責任

出差外派

無需出差外派

上班時段

日班

休假制度

週休二日

可上班日

不限

需求人數

1人

條件要求

工作經歷

6年以上

學歷要求

碩士

科系要求

不拘

語文條件

不拘

擅長工具

不拘

工作技能

不拘

其他條件

未填寫

聯絡方式

聯絡人

Jennie
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