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公司介紹
產業描述
IC 設計業
電話
02-87529000
員工人數
暫不提供
地址
新竹縣竹北市環科一路3號十樓
公司簡介
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Progress takes many forms. Sometimes, progress is the breakthrough solution that helps the world leap forward. Other times, progress is the result of unforeseen obstacles that make us pause and think about what we need to do differently in order to do things right. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of data infrastructure semiconductor technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. To learn more, visit: www.marvell.com.
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主要商品 / 服務項目
https://www.marvell.com/
福利制度
Marvell hires the best of the best. We are the most innovative company working in the semiconductor industry today. We have an outstanding history of delivering next generation products that are revolutionizing the way the world works, and we’re looking for smart, talented, like-minded people to join us on the adventure. If you want to achieve great things, then we want to talk with you. And we want to reward you for striving for the best. We not only push the envelope in terms of product development, we foster your personal and professional growth by providing an advanced research environment where your work can really make a difference. You’ll be shoulder to shoulder with some of the most talented people in the world and offered the opportunity to help set the standard that other companies want to follow. At Marvell, we attract the top talent in the industry. And we know that top talent expects and deserves stellar benefits. We offer one of the most robust benefits packages available today, designed with your particular needs in mind. Of course you’ll be offered a competitive salary, plus incentive stock options, but that’s just the start. You’ll also be offered: * Insurance Coverage: Labor Insurance, National Health Insurance, Group Insurance * Pension Plan * Incentive Plan * Employee Stock Purchase Plan * Employee Stock Option Plan * Restricted Stock Option Plan * Good Vacation and Leave Plan * Medical/Health Club Reimbursement Plan * Competitive Training and Education Plan * Employee Welfare Committee Benefits * More...
工作機會
10/05
Seeking a Mixed Signal designer to be part of a key team designing highly sophisticated CMOS transceiver/SERDES products.
*Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.
*Should be comfortable carrying out layout activities in nanometric technologies and be able to supervise physical design.
*Should be able to work in the lab independently or with test engineers to characterize, debug and validate designs.
*Would be required to generate design related documents, application specifications etc. and may support customers and FAEs as needed.
*May be required to interface with digital and SOC teams to facilitate design integration and cross-functional verifications.
8/14
*Develop and optimize test methodologies for optical/electrical performance validation (e.g., IV, TIA/DRV behavior, MZM control, PD characterization).
*Design, set up, and maintain automated and semi-automated optical/electrical test stations.
*Cross-functional collaboration with design, packaging, and process teams to define test requirements and ensure design-for-test (DfT) alignment.
*Support test readiness for new product introduction (NPI) and mass production ramp.
*Interact with external vendors, contract manufacturers, and FA teams to resolve issues and improve test quality.
*Document test processes, procedures, and technical learnings in a structured, clear manner.
10/05
ASIC design engineer responsible for post-RTL design flow.
He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs.
The responsibilities include but are not limited to.
• Improve the design methodology and flow.
• Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications.
• Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines.
• Provide support to the product teams, for both pre and post-silicon
8/04
ASIC design verification engineer responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, test case development, and execution.
As a senior member in the team, he/she will focus on improving the design verification methodology and flow. Work cross-function with analog and DSP teams to achieve high-quality analog mixed-signal verification.
The responsibilities include but not limited to:
(1) Architect and develop UVM-based testbenches for complex IP and SoC verification.
(2) Define and drive verification plans, test strategies, and coverage goals.
(3) Collaborate with design, AMS, and validation teams to ensure functional correctness.
(4) Lead debug efforts, root cause analysis, and regression triage.
(5) Guide and mentor junior DV engineers in UVM methodology and best practices.
(6) Contribute to the development of reusable verification components and infrastructure.
(7) Continuously improve verification processes, tools, and automation frameworks
9/08
* Design and develop firmware for the Marvell's diverse portfolio of Compute, Storage and Custom ASIC solutions.
* Partner closely with the hardware engineering team to bring up, test and validate the hardware reference platforms for our Compute, Storage, and Custom ASIC product lines.
* Design and implement software/firmware for Management Controllers within Marvell's hardware reference platforms to improve the testability and validation of Marvell Silicon solutions.
* Support the software/firmware qualification efforts by creating comprehensive test cases, contributing to test automation, and advancing our CI/CD pipeline development and processes.
10/05
We are seeking a highly experienced and detail-oriented Senior Hardware Board Development Engineer with 10–15 years of hands-on experience in hardware system design. This role focuses on the development of evaluation boards (EVBs) and customer reference boards (CRB) for advanced SoC/ASIC platforms, including board-level architecture, high-speed signal design, and system bring-up.
You will work closely with SoC/ASIC design teams, firmware engineers, and validation teams to deliver robust reference platforms for internal and customer use. The ideal candidate has deep expertise in DDR4/DDR5, PCIe Gen4/5/6, high-speed SerDes, and power delivery networks, along with strong debugging and lab skills.
Responsibilities
* Lead the design and development of SoC/ASIC evaluation boards, including schematic capture, PCB layout review, and component selection.
* Perform board bring-up, signal integrity validation, and system-level debugging.
* Collaborate with cross-functional teams to support SoC/ASIC validation and customer reference designs.
* Conduct SI/PI simulations and optimize high-speed interfaces (DDR, PCIe, Ethernet).
* Generate technical documentation including schematics, BOMs, test procedures, and design guides.
* Interface with vendors and manufacturing teams for prototype builds and production support.
10/05
You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
Every day, you’ll be working hands-on to triage workflows, whether you’re running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc.
There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it’s your responsibility to review completed runs for errors or create optimizations from successful runs.
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