Sr. Staff Engineer, Design Verification

08/04更新
應徵

工作內容

ASIC design verification engineer responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, test case development, and execution. As a senior member in the team, he/she will focus on improving the design verification methodology and flow. Work cross-function with analog and DSP teams to achieve high-quality analog mixed-signal verification. The responsibilities include but not limited to: (1) Architect and develop UVM-based testbenches for complex IP and SoC verification. (2) Define and drive verification plans, test strategies, and coverage goals. (3) Collaborate with design, AMS, and validation teams to ensure functional correctness. (4) Lead debug efforts, root cause analysis, and regression triage. (5) Guide and mentor junior DV engineers in UVM methodology and best practices. (6) Contribute to the development of reusable verification components and infrastructure. (7) Continuously improve verification processes, tools, and automation frameworks

工作待遇

待遇面議

(經常性薪資達 4 萬元或以上)

工作性質

全職

上班地點

新竹縣竹北市

管理責任

不需負擔管理責任

出差外派

無需出差外派

上班時段

日班

休假制度

週休二日

可上班日

可年後上班

需求人數

1~2人

條件要求

工作經歷

8年以上

學歷要求

碩士

科系要求

電機電子工程相關

語文條件

英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通

擅長工具

不拘

工作技能

其他條件

(1) Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, EE or related field. (2) 8+ years in ASIC/SoC/IP design verification. (3) Expert in UVM and SystemVerilog. (4) Strong understanding of digital and AMS verification flows. (5) Experience with simulation tools (e.g., VCS, Questa, Xcelium). (6) Familiarity with scripting languages (Python, Perl, Tcl) for automation. (7) Knowledge of SerDes, high-speed interfaces, or calibration is a strong plus. (8) Proven leadership and mentoring capabilities. (9) Strong problem-solving and debugging skills. (10) Excellent communication and cross-functional collaboration.

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Marvell_邁威爾科技有限公司 企業形象

福利制度

Marvell hires the best of the best. We are the most innovative company working in the semiconductor industry today. We have an outstanding history of delivering next generation products that are revolutionizing the way the world works, and we’re looking for smart, talented, like-minded people to join us on the adventure. If you want to achieve great things, then we want to talk with you. And we want to reward you for striving for the best. We not only push the envelope in terms of product development, we foster your personal and professional growth by providing an advanced research environment where your work can really make a difference. You’ll be shoulder to shoulder with some of the most talented people in the world and offered the opportunity to help set the standard that other companies want to follow. At Marvell, we attract the top talent in the industry. And we know that top talent expects and deserves stellar benefits. We offer one of the most robust benefits packages available today, designed with your particular needs in mind. Of course you’ll be offered a competitive salary, plus incentive stock options, but that’s just the start. You’ll also be offered: * Insurance Coverage: Labor Insurance, National Health Insurance, Group Insurance * Pension Plan * Incentive Plan * Employee Stock Purchase Plan * Employee Stock Option Plan * Restricted Stock Option Plan * Good Vacation and Leave Plan * Medical/Health Club Reimbursement Plan * Competitive Training and Education Plan * Employee Welfare Committee Benefits * More...

聯絡方式

聯絡人

Selena Yu

其他

https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Hsinchu-City/Senior-Staff-Engineer--Design-Verification_2501401

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