佳易科技股份有限公司

-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Ethernet 3. Can solve complex, novel and non-recurring problems.

1.Gb Ethernet PHY IP Development on 0.13um Process 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library

- Design/development of SoC subsystem blocks. - Responsible for SOC system Integration/Verification - Generate detailed micro-architecture technical specifications and systems requirements and deliver the design - Work closely with verification team to develop verification plans and actively participate in debug phase - Work hands-on and own their design through the full SoC/ASIC development process from specification, RTL implementation, verification, synthesis timing closure, emulation and post silicon bring up

A. Familiar with Standard Cell Circuit Design, verification of functionality, performance and power improvement methodology. B. Calculate cost( tools and man power ) of developing full set standard cell libraries C. Be able to judge and select required cells for target standard cell libraries D. Capable of defining timing specification for target standard cell libraries E. Plan and evaluate the Return Of Investment of developing new Standard Cell Library Skills & Competency Requirement: 1. Good fundamental knowledge on digital circuit design 2. Good team work personality 3. Familiar with library characterization and logic synthesis flow 4. Has experience of developing and verifying standard cell libraries 5. Knowing how to optimize standard cell libraries

1.0.13um & 0.18um ASIC Memory cell and Memory Compiler Development 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library

1.Gb Ethernet Controller IP Development on 0.13um Technology 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library

1. Supervise system engineering div. to instruct and guide members successfully completing assigned engineering works within preset time line. 2. Organize and plan 3 yrs man power requirement to fulfill company KPI. 3. Pick up core technologies from R&D div. to create various system level products according to market/customers demand, covering HW, SW and testing working scopes to transfer the design over to customers for mass production. 4. Allocate resources to fix system related issues on time. 5. Communicate with R&D supervisor to resolve cross over engineering issues. 6. Report working progress to management regularly.

Seeking a self-motivated, team-oriented system board design engineer to develop medical and healthcare products. This position requires experience in hardware architecture, sensors interface, signal conditioning and power design. A successful candidate will have a good knowledge of medical device board design and implementation. In addition, this candidate will have a good working knowledge of signal and power supply design as well as sensor interface, signal amplification, and use of filter and ADC on-board. Experience with PCB design tools (Cadence/Mentor PCB design and analysis). Expertise in design for optimum signal and power integrity as well as hands-on lab measurements experience is a must. Candidate should have a thorough understanding of hardware development methodologies in medical/healthcare products to achieve a first pass design success. The scope of work includes but is not limited to: • Interface in cross functional teams to ensure the design meets all firmware, diagnostic and system level requirements. • Participate in architecture definition and lead designing of medical and healthcare products. Complete ownership of hardware through the product life cycle. • Perform detailed verification of the design in lab to ascertain the design margins. • Document and communicate results with cross functional counterparts. • Debug design issues and capture reports. • Experience in designing high volume and cost sensitive products (keeping manufacturability challenges in mind) • PCB back-end process: defining stack-up and via technologies, part placement, setting design constraints • Works proactively with cross functional team members during design and verification Desired Skills & Competency Requirement: • Self-motivated. Desire to take on challenges. Result-driven and details oriented. • Strong interpersonal and communication skills are a must. • Good PCB design experience on signals routing guideline and review design for EMI/ESD protection. • Had previously completed system and board design for medical/healthcare products (important) • Added advantage for experience with medical/healthcare wearables product development • Experience developing medical devices within FDA, ISO, and IEC requirements and guidelines including risk analysis and quality assurance. • Fluency with schematic design. Cadence toolsets experience preferred. • Practical experience with design/measurement tools and real time/sampling scopes • Cadence Sigrity, Allegro Power-Aware SI, Mentor Graphics HyperLynx, Altium (will be a plus) • Basic knowledge of controls, motor and sensors theory with some coding ability (python, java, or C++) is desired • Working knowledge of various standards with regards to PCB manufacturing and assembly techniques • Creates moderately complex printed circuit board layouts and documentation from schematics using Computer Aided Design (CAD) tools • Support Bill of Material development for new and updated schematics • Expert at troubleshooting and debugging prototype hardware/software

-Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. -Experience in analog IP development that include SERDES, ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies. -Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an added advantage. -Preferably done some test characterization, measurement and compliance in previous employment 1.Must have in-depth knowledge in circuit and logic IP design flow with hands-on experience in design and development, mixed signal design and simulation verification, IP test/characterization, low power high speed design methodology. Scripting in Perl, TCL, Unix, Linux 2.The ability to work with multiple team members 3.Working experience in EDA tools such as Synopsys Design Compiler, Physical Compiler, PrimeTime etc is a plus.

The Business Development will be responsible for the overall management of the Company’s business development organization. Responsibilities: • Serve as a key member of the executive team that sets the company’s strategic direction. • Spearhead business development and marketing initiatives that are consistent with the company’s overall strategy. • Manage multiple business initiatives in a start-up environment. • Revenue generation and strategic partnerships development and management. • Manage complex contract negotiation and work with legal counsel as required. • Work closely with Sales team and win early customers with limited support. • Be the driving force in the development of the work ethic, culture and values of the sales and business development group. Through personal example, establish the style and approach which will characterize the Company’s dealings with the marketplace. • Manage the ASIC design services business and the IP development • Manage the IOT and AI chips as our next growing product line. • Develop partnership with IP vendors and foundries. • Provide close support to the Engineering team. • Identify and qualify Foundries for partnership and alliances. Ability to identify potential deals and develop the tactics and teams needed to bring them to fruition. You will actively lead the business development function in an effective, aggressive manner. At the same time, you will also be expected to be a contributor to the management of the company as a whole, as a member of the senior management team. These needs, essential at this stage of the company’s development, establish the necessary professional background and experience parameters for the successful candidate.

【About Us 】 KeyASIC Berhad was incorporated in Malaysia in year 2005. In 2006, we were awarded with Multimedia Super Corridor (MSC) Status by Malaysia Digital Economy Corporation (MDEC). We started off with the design of IP, ASIC and SoC. We now have more than 10 SoC’s manufactured in Silterra 0.18um, 0.16um and 0.13um process technologies. In 2009, we were listed on the main board of KLSE. Khazanah and CIMB are our main investors. Our core competency is the capability to design SoC and ASIC from system specification and architectural level to GDSII. The key differentiator is our expertise in designing high performance, low power consumption and smaller integrated circuits. We are building up to be a leader in IoT. KeyASIC Berhad focuses on improving lives by providing IoT-enabling technology in the area of healthcare, wellness applications, consumer electronics, industrial equipment and many other applications. Leverage on KeyASIC’s integrated microcontrollers and wireless connectivity for continual technology improvement. In addition to the current products, we have the ability of Artificial Intelligence (AI) chip technology and that can be applied to the healthcare, surveillance among other industries. KeyASIC will continue to invest in research and development of products based on IoT, Block Chain and Artificial Intelligence. Our offices locations – Singapore, Malaysia, Taiwan, Shanghai and Beijing. 【Responsibilities 】 • Actively source candidates using a variety of search methods to build a robust candidate pipeline (eg. LinkedIn, Monster, etc) • Screen candidates by reviewing resumes and job applications, and performing phone screenings • Stay abreast of recruiting trends and best practices