找頭鹿 智能客服
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公司介紹
產業描述
IC設計公司
電話
暫不提供
員工人數
755人
地址
台北市內湖區瑞光路 335 號 14 樓 (內湖科技園區)
公司簡介
譜瑞科技股份有限公司為一專供多種普及顯示器以及個人電腦、消費性電子產品與顯示面板所使用之高速訊號傳輸介面標準之混和訊號IC晶片之領導供應商。譜瑞公司成立於西元2005年為一無自有晶圓廠之半導體公司，並於西元2011年股票在台灣櫃檯買賣中心正式掛牌交易(股票代號: 4966)。譜瑞公司的IC晶片產品組合可支援顯示產品，儲存設備以及介面應用所使用之HDMI™, DisplayPort™, SATA, 與USB等傳輸介面規範之IC晶片成長需求。 Parade Technologies, Ltd. is a leading supplier of mixed-signal ICs for a variety of popular display and high-speed interface standards used in computers, consumer electronics and display panels. The fabless semiconductor company was founded in 2005 and publicly listed on Taiwan’s GreTai Securities Market (GTSM) in 2011 (stock code: 4966). Parade’s portfolio of IC products serves the growing demand for HDMI™, DisplayPort™, SATA, and USB ICs for display, storage and interface applications. 「響應參與【產學研工程人才實務能力卓越基地計畫】工程人才網路就業媒合平台」IDBET_104
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主要商品 / 服務項目
High Speed Interface ICs - PCI Express / SATA - USB - DisplayPort - HDMI - Protocol Converters Display and Touch Integrated System ICs - Embedded DisplayPort(eDP) Timing Controllers (Tcons) - Display Panel Source Drivers - Tcons with Embedded Source Driver (TED) - Touch & Display Driver Integrated (TDDI) - DisplayPort LCD Monitor Controller TrueTouch ICs - TrueTouch Touchscreen Controller
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福利制度
法定項目
其他福利
<日常照顧與保障> 勞保、健保 公司給付之團體保險(含意外、醫療險壽險、旅行平安險、附加意外險等) 定期勞工健康檢查 <福利與獎酬> 年終獎金 現金分紅 員工配股 優渥推薦獎金 生育禮金 季慶生會 尾牙聚餐 員工秋遊 年節禮品 周年紀念品 通勤補助、竹北-台北交通車、桃園-台北交通車 <假勤制度> 週休二日 優於勞基法之特休
工作機會
9/22
1. Support customer projects from design-in, design-through to mass-production.
2. Team work with AE, FAE, RD and QA to solve problems.
9/22
-Working with IC design team on IC bring up and electrical verifications.
-Develop evaluation hardware platforms, reference schematic and PCB board verification.
-BOM cost and competition analysis.
-Technical support for customer projects along with AE/DE/SW/FW/QC engineers.
9/22
1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
2. Collaborate with other team members to integrate the block with the full chip
3. Use Verilog to design and System Verilog for block level verification
4. Assist the Verification team in reviewing and debugging test cases
5. Run LINT and CDC checks on the RTL code and fix accordingly.
6. Assist with synthesis and FPGA emulation.
9/11
1.5+ years' experience with MS in EE or CS
2.Hands on silicon design and bring up experiences
3.Experiences with data communication protocols such as PCI Express, SuperSpeed USB, SATA, etc.
4.Experiences in mixed signal design with good understanding of analog circuit design
5.Design experience with PCIe 3.0 and 4.0 is a plus
9/19
1. 5+ years experiences with MS in EE
2. Hands on experiences on the design and validation of wireline high speed silicon
3. Experiences with strong design capability for the 10Gbps+ wireline data transfer
4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus
9/18
1. 5+ years experiences with MS in EE
2. Hands on experiences on the design and validation of wireline high speed silicon
3. Experiences with strong design capability for the 10Gbps+ wireline data transfer
4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus
9/22
1. Analog circuit design and verification, such as OPAMP, Bandgap, ADC/DAC, PLL, and etc.
2. Power management circuit design and verification, such as LDOs, Charge Pumps, Switching Regulators, Gamma reference, and etc.
3. Whole chip integration with mixed-signal circuit.
4. HV I/O and ESD design.
9/25
1. Architect a major block of an ASIC and write a microarchitecture specification (MAS) for the block
2. Collaborate with other team members to integrate the block with the full chip
3. Use Verilog to design and System Verilog for block level verification
4. Assist the Verification team in reviewing and debugging test cases
5. Run LINT and CDC checks on the RTL code and fix accordingly.
6. Assist with synthesis and FPGA emulation.
9/23
1. Responsible for display and image processing algorithm development.
2. Participate in system architecture definition, algorithm developing and evaluation, algorithm implementation and simulation.
9/25
1. Responsible for display and image processing algorithm development.
2. Participate in system architecture definition, algorithm developing and evaluation, algorithm implementation and simulation.
9/15
1. In charge of implementing digital circuits for mixed-signal design (from gate level netlist to GDS)
2. Performing daily tasks including floor-plan, CTS, PnR, STA, Power budget, IR-drop / EM / Cross-talking analysis and sign-off.
3. Estimation of efforts and schedules for assigned project.
4. Close cooperation and interaction with other design teams in different company sites.
8/17
1. In charge of implementing digital circuits for mixed-signal design (from gate level netlist to GDS)
2. Performing daily tasks including floor-plan, CTS, PnR, STA, Power budget, IR-drop / EM / Cross-talking analysis and sign-off.
3. Estimation of efforts and schedules for assigned project.
4. Close cooperation and interaction with other design teams in different company sites.
9/25
1.5+ years' experience with MS in EE or CS
2.Hands on silicon design and bring up experiences
3.Experiences with data communication protocols such as PCI Express, SuperSpeed USB, SATA, etc.
4.Experiences in mixed signal design with good understanding of analog circuit design
5.Design experience with PCIe 3.0 and 4.0 is a plus
9/22
1. Support customer projects from design-in, design-through to mass-production.
2. Team work with AE, FAE, RD and QA to solve problems.
9/23
1.Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board
2.Support Customer projects design-in stage to mass-production.
3.Support Customer projects design review (Schematics, layout, CTS report)
4.Team work with RD, AE and QA on debugging and problems solve.
9/22
-Working with IC design team on IC bring up and electrical verifications.
-Develop evaluation hardware platforms, reference schematic and PCB board verification.
-BOM cost and competition analysis.
-Technical support for customer projects along with AE/DE/SW/FW/QC engineers.
9/22
【Position Goals】
1.Ensure successful delivery and excellent technical support of in-cell notebook projects at target panel vendors and notebook ODMs.
2.Establish in-depth technical relationships with panel engineers and establish Parade as vendor of choice for notebook in-cell solutions.
3.Establish trust and respect with key engineering stake-holders.
【Main Responsibilities】
1.Co-work with Parade Sales/FAE/Marketing to secure design wins and panel qualification.
2.Ability to work in tandem with a display FAE to execute in-cell designs from kick-off to mass production.
3.Work with AE and RD teams to debug customer field issues
4.Manage project-level details and proactively mitigate risks for customer projects
5.Provide frequent onsite support and debug to ensure program success and customer satisfaction
6.Become the trusted expert advisor for customer panel engineers and project teams by doing what's best for the customer – strong bias to action.
7.Respond to customer RFQs and product technical information.
9/22
1.Develop validation plans, execute system-level qualification tasks, and conduct stress tests to evaluate product reliability.
2.Support compatibility testing for PD, HUB, and related products.
3.Analyze root causes and provide relevant debugging information to assist R&D in resolving issues.
4.Summarize qualification results and compile the final QA report.
5.Support the marketing and FAE team in analyzing field failures and provide feasible solutions based on findings.
9/25
1.Partnership and reference design engagement
2.Engage with key OEM/panel customer and major SOC vendors to define new products in display Tcon/SD solutions
3.Work with cross-functioning team from define phase to POC phase, design-in phase, then achieving mass production.
4.Coordinating cross-departments and multi-functional teams.
5.Promotion activity, plan, prepare and deliver presentations.
6.Collect market data and conduct competitive analysis from field side.
9/25
※This position requires working in Taipei 2–3 days each week.
1.Partnership and reference design engagement
2.Engage with key OEM/panel customer and major SOC vendors to define new products in display Tcon/SD solutions
3.Work with cross-functioning team from define phase to POC phase, design-in phase, then achieving mass production.
4.Coordinating cross-departments and multi-functional teams.
5.Promotion activity, plan, prepare and deliver presentations.
6.Collect market data and conduct competitive analysis from field side.
9/23
1. Perform internal audits
2. Arrange the annual self-assessment for each department and prepare the self-assessment report
3. Support the Company in complying with requirements for legitimizing listing and operating in Taiwan
4. Assist in holding the Annual General Meeting and prepare all necessary documents
5. Assist in preparing the required documents for Board meetings and Audit Committee meetings
6. Assist in preparing the Sustainability Report and handling ESG related tasks.
7. Assist in handling the corporate governance evaluation
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