Sr. ASIC Design Engineer(台北)

1. BA/MS degree and 5+ years of relevant work experience. 2. Demonstrate knowledge of Verilog for chip design and verification. 3. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug. 4. Understanding of digital design and verification practices. 5. Be able to take a specification, write RTL and simulation vectors to verify their RTL. 6. One prior RTL design is a requirement. 7. Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.