5G Senior Digital Circuit Design Verification Engineer(土城/新竹)

1. Verilog/System-verilog, C/C++ language, TCL, CSHELL, MAKEFILE, Perl, Python. 2. Knowledge and hands-on experience of SystemVerilog and UVM. RTL is a plus. 3. Build the UVM testbench from a scratch. 4. Building the testbench by purely SV is acceptable. 5. Ability of building the SoC-level testbench including mounting the VIP and BFM is a plus. 6. Verify the design via the random pattern by using the UVM. 7. Experience of creating UVM sequences on IP-level and SoC-level. 8. Aiming on raising the quality of design. Hands-on experience of the functional coverage and code coverage. 9. Knowledge/experience of wireless/wireline communications physical layer design is a plus 10. Team-oriented and capable of working closely with the system engineers and other designers. 11. Timely-fashion-deliver and can-do-attitude are big plus.