1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.
待遇面議
(經常性薪資達 4 萬元或以上)
不拘
1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.
1.表定上班時間:09:00-18:00,本公司實施彈性上班制 : 08:00-10:30 均為上班時段 2.每月可申請兩天work from home,有特殊需求者可增加天數 3.到職首年即享6天特休(含勞基法滿半年之3天特休) 4.每年享優於勞基法之4天彈性休假 5.每年享優於勞基法之10天有薪病假 6.依法勞保/健保/勞退提繳,並享有免費團險 7.享三節獎金或禮品 8.每月定額交通費補助與每年員工健康檢查補助 9.提供社團活動經費補助 10.每季定期舉辦員工聚餐 11.每季定期舉辦慶生聚會,不定期下午茶Happy Time 12.無限提供星巴克膠囊咖啡&各項零食 13.全面採用人體工學座椅