職務說明 1.3+ years experiences in ASIC/SOC IC design, sample verification 2.Experience on RTL / Verilog design, synthesize, formal check, simulation 3.Familiar with ARM-Cortex CPU (or 32-bit CPU) bases ,mixed signal SOC design is a plus 4.Experience on FPGA design and verification/validation is a plus 5. Experience to plan and execute IC verification in Lab and write test report, and able to outsource verification board design 6.Able to write block design or small IC specifications 7.Able to write specification and reports in both Chinese and English 8.English communication capability is a must 9. Team work oriented is a plus 10. Able to work across different department or functions to optimize ASIC design
待遇面議
(經常性薪資達 4 萬元或以上)
Verilog、VHDL、FDGA 1. Skilled Verilog HDL / VHDL coding and simulation tool 2. Synopsys synthesis tool. 3. Perl/C/shell coding. 4. Skilled at FPGA. 5. Skilled in Architecture Define. 6. Experience in MCU design 7. Proven IC design with embedded CPU SOC.
◆ 分紅 / 配股 1.員工紅利 2.員工配股 3.員工認股 ◆ 獎金 / 禮品類 1.年終獎金 2.三節禮金/禮品 3.勞動節獎金/禮品 4.生日禮金/禮品 ◆ 保險類 1.勞保 2.健保 3.員工團保 4.眷屬團保 5.意外險 ◆ 制度類 1.伙食費 2.介紹獎金 3.績效獎金 4.完整的教育訓練 5.順暢的升遷管道 ◆ 請 / 休假制度 1.週休二日 2.特休/年假 3.陪產假 ◆ 其他 1.美式人性化管理 2.員工停車位 3.免費健康檢查 4.特約商店 5.預享半個月薪資 6.彈性上、下班 7.每季員工溝通座談會 8.提供加班免費晚餐 ◆ 補助類 1.結婚禮金 2.生育津貼 3.員工進修補助