IP Memory Design Engineer (Hsinchu) (3059285)

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446697376843 【Job Description】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. 【Job Summary】 This position involves designing and implementing Low-power, High Performance, area-efficient embedded memory (CPUL1/L2, SRAM, register files, etc.) circuits and architectures. Position will be located in APAC-TW metropolitan region. 【Responsibilities】 Develop memory architectures and circuit implementation techniques. Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation. 【Qualifications in the following areas are preferred】 - 3+ years of academic or professional experience designing embedded memories for SoC applications - Strong Technical expertise in CPUL1/L2, Compiler SRAM/Register File architectures and advanced custom circuit implementations. - Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation - Physical implementation (layout) and layout supervision - Advanced technology nodes 【Qualifications in the following areas are a plus】 - Experience with tight pitch-matched memory layout designs - Understanding of physical implementation impact on circuit performance - Familiarity with variation-aware design in nano-meter technology nodes - Experience with low power design features and flows