(2026 New College Grad) Analog Design Engineer(Power)_(限即將畢業、剛畢業或工作經驗一年以下者)

Tasks & Responsibilities Responsibilities may include but are not limited to: • Creating transistor-level analog circuits to meet performance specifications • Verifying designs using circuit-level and behavioral-level simulations • Supervising and reviewing circuit layout • Performing AMS simulations for top-level verification • Modeling DC-DC switching regulator behavior using Simplis or Verilog-A • Reading and understanding Verilog RTL code • Writing circuit documentation and test plan • Validating and debugging circuit performance in the lab • Collaborating with cross-functional teams including applications, test engineering, and other design groups. Qualifications & Skills • Minimum qualification: o Bachelor’s degree in Electrical Engineering or related field o Strong understanding of analog IC design fundamentals o Solid knowledge of basic analog circuit topologies and layout principles o Effective written and verbal communication skills in English o Strong teamwork and collaboration skills • Preferred qualification: o Master’s degree in Electrical Engineering or related field o Research experience related to IC design o Familiarity with Cadence design environment and analog simulation tools. o Experience with Simplis is a plus o Knowledge of Verilog-A, Verilog-AMS or WREAL modeling is a plus o Understanding of Verilog hardware description language is a plus o Proficiency in at least one scripting language (Python, shell-scripting, etc.). 歡迎身心障礙者應徵