T－Engineer for IC design（遠端）

1. MSEE with minimum of 2 years, or BSEE with minimum of 3 years experience and good understanding in digital ASIC/SOC design work. 2. Experience of RTL design in ASIC 3. Experience of TO flow, especially for Front End 4. Good experience of EDA tools, like Lint, CDC check, PrimeTime PX 5. Good document for designed module 6. Good co-work with DV team for IP verification work 7. Good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas. 8. One or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol is plus