【知名科技品牌外商】ASIC Verification Engineer (Contractor) (ID: 668670)

1. Development of ASIC verification plans. 2. Development of UVM tests for ASIC verification to achieve comprehensive coverage. 3. Working with ASIC design and architecture teams to understand functionality. Requirements : 1. Bachelor’s degree in Electrical Engineering or Computer Science. 2. Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred. 3. Knowledge of ARM AMBA Bus protocols 4. Knowledge of System Verilog and UVM verification methodology. 5. Four-year (Master) or six-year (Bachelor) experiences on design verification with UVM platform.