Senior Design Verification (DV) Engineer

【Basic Qualifications】 · Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or related fields. · 2+ years of experience in ASIC/FPGA Design Verification. · Proficiency in System Verilog, including testbench and assertion development. · Experience with industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). · Good knowledge of UVM methodology and testbench architecture. · Familiarity with scripting languages (e.g., Python, Perl, Shell) for verification automation. · Good communication skills and ability to work effectively within a team environment. 【Preferred Qualifications (Nice to Have)】 · Experience with SoC-level or Subsystem-level verification, including CPU, Cache, AXI/AHB/ACE bus protocols. · Hands-on experience in Formal Verification (Synopsys VC Formal, Cadence JasperGold, etc.). · Familiarity with low-power verification (UPF/CPF) flows. · Knowledge of post-silicon bring-up or emulation/simulation co-verification. · Exposure to security verification, automotive safety (ISO 26262), or functional safety methodologies.