Senior Layout Engineer 資深佈局工程師

Thorough knowledge of industry standard EDA tools and others such as Virtuoso.... Experience in high performance analog layout in advanced CMOS process. Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Great attention to detail, communication skills, well organized, patience in work. Requires self-starter with the ability to define and adhere to a schedule.