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共 260 筆
10/17
1. MOSFET device research and development, especially Trench MOSFET/ SGT/ SJ.
a). Define device layout design and product design rule
b). TCAD simulations to build device structure
c). Device measurement
d). DOE plan for MOSFET new product
2. Interface with Product engineer and Marketing.
3. EFA/ PFA for trouble shooting
4. Build related patent for new design
10/17
Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.
10/17
1.依照電子工程師及專案需求，進行電路板的Placement, Routing, Gerber out
2.PCB零件建立與資料庫維護
3.Gerber file 製作、發行及維護
4. 負責與 PCB 板廠溝通PC板製程等相關工程詢問
6. 負責與外包 Layout house對接跟進 PCB Layout 專案工作
10/17
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
2. Responsible for physical verification including DRC, LVS and ESD checking.
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10/17
Analyzing voltage drop across the power grid under different operating conditions.
Evaluating current density in metal interconnects and reliability concerns.
Design, analyze, and improve power grids.
Cross-functional collaboration – working with design, package, and verification teams.
Automation and Flow Development – gaining hands-on experience in scripting to improve design efficiency.
10/17
1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation.
2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS.
3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus.
4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus.
5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.
10/17
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
2. Responsible for physical verification including DRC, LVS and ESD checking.
10/17
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
2. Responsible for physical verification including DRC, LVS and ESD checking.
10/17
1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process.
2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment.
3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification.
4. Co-work with front-end design team for the logic, clock and timing optimization.
5. Co-work with package team for the substrate design and SIPI simulations.
10/17
1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process.
2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment.
3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification.
4. Co-work with front-end design team for the logic, clock and timing optimization.
5. Co-work with package team for the substrate design and SIPI simulations.
10/17
【本職缺可透過104應徵，也歡迎直接至穩懋官方網站投遞，增加履歷曝光度】請至穩懋官方網站投遞個人履歷表，此職缺履歷登錄網址：
https://www.winfoundry.com/WinTalentPool/JobRequirement/Edit/16
1. 客戶光罩製程規則(DRC)驗證處理
2. Cadence電路佈局軟體操作暨開發
3. 製程規則(DRC/LVS)程式開發撰寫
4. 協助新製程開發.
10/17
1. 需要熟悉Virtuoso & Laker 的操作使用.
2. 可獨立解決DRC,ERC,LVS error.
3. 須了解Process.
4. 負責IC layout and verify,確保IC layout符合Circuit Designer設計需求.
5. 要有良好的工作態度和EQ.
6. 可配合加班
10/17
IC Block fully Layout.
(1) 熟悉 layout tools(Virtuoso)
(2) 熟悉 verify tools(calibre)
(3) 熟悉 DRC/LVS debug
期滿視狀況決定是否續約或轉正職。
相關工作經歷 2年以上
學歷要求 專科以上
10/17
1. 負責產品之佈局、DRC、LVS， 並產生供光罩製作之data base。
2. IC analog/digital full layout.
10/17
【本職缺可透過104應徵，也歡迎直接至穩懋官方網站投遞，增加履歷曝光度】請至穩懋官方網站投遞個人履歷表，此職缺履歷登錄網址：
https://www.winfoundry.com/WinTalentPool/JobRequirement/Edit/12
1. 光電專利技術趨勢分析(70%)
2. 前案檢索
3. 專利申請與答辯策略
10/17
1.DRC command file 撰寫
2.QA flow製作及檢驗以確保品質
3.deck guideline 製作及檢驗以確保品質
4.客戶DRC問題解答
5.DRC教育訓練
6.EDA Vendor Contact Window
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