• Lead imager package product design activities including: schematic and package netlist definition; package circuit layout; package simulations; package design review and approval; and package product performance verification. • Provide direct design support for imager package product designs including wire bond BGA/LGA/PGA, MCP (multichip package), flip chip package and WLCSP (wafer level chip scale package). • Work directly with Product Design, Design Integration, Product Engineering, Test Engineering, Applications Engineering, Hardware Development, Marketing, Packaging R&D, Packaging NPD, Purchasing, OSAT’s, and key package material suppliers.
待遇面議
(經常性薪資達 4 萬元或以上)
• Bachelor or master degree in Electrical Engineering, Mechanical Engineering, or Engineering related. • 8+ years experience in package and/or hardware system design, assembly process engineering, and new product development. • Package/PCB layout experience using Cadence APD/SIP required. • Signal/Power/Ground integrity experience and familiarity with simulation tools such as Cadence Sigrity Package Assessment, ANSYS Q3D, and ANSYS HFSS. • Mechanical design experience using AutoCad and Solid Works. • Solid understanding of packaging assembly process and material properties. • Experience with thermal and mechanical stress simulation using finite element analysis. • Strong project management and problem solving skills required. • Able to work independently and interact with multinational team members. • Bilingual in English and Mandarin Chinese.
Transportation Allowance Meal Allowance Car Plan Annual Leave and 15 days Supplementary Leave Festival Gift Group Insurance Health Insurance Labor Insurance Welfare Program