FPGA 研發資深工程師

1. 熟悉FPGA - Familiar with Verilog RTL design. - Familiar with RTL simulation, timing analysis using Xilinx Vivado Design Suite. - Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. - Familiar with Xilinx FPGA serdes IO, and select IO. - Familiar with Xilinx IP design and packaging. - Familiar with at least one Xilinx FPGA device. - Familiar with Xilinx HLS is a plus. - Familiar with Xilinx Zynq SoC is a plus. 2. 熟悉影像方面的高速介面(HDMI/ eDP/3G-SDI/12G-SDI) 、DDR高速介面、I2C、UART、SPI等介面應用。 3. 良好的溝通協調能力 4. 具醫療影像及色彩處理經驗優先錄取 5. 擅長Xilinx FPGA Vivado tool