【2026 RDSS研發替代役】Signal and Power Integrity Engineer

歡迎2026年畢業並正在找尋研發替代役的同學申請! What You'll Be Doing: • Post-layout model extraction for project review sign-off • pre-layout model extraction for DOE • Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout • Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts • Work w/ Application Engineering teams to support customers w/ SI/PI questions • Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc. What We Need To See: • MS in EE and majoring in SI/PI technology or equivalent experience, • Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge • Know how to use ANSYS HFSS/Q3D/SIwave/Designer, Synopsis HSPICE, Cadence PowerSI, and Keysight ADS • Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes • Familiarity with transient simulation in tools and understanding of eye diagram methodology • Exposure to lab measurements including VNA & TDR, and oscilloscope experience • Passionate about SI/PI work Ways To Stand Out From The Crowd: • SI analysis flow including frequency and time domain simulation • PDN analysis flow including model generation and time domain simulation • PSIJ Analyses involving co-simulation of circuits and PDN models • Experience w/ Matlab, Python, VBS, and C • RF/microwave engineering; EMI/RFI analysis capability 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。