(2026 New College Grad) Analog Design Engineer(High Speed)_(限即將畢業、剛畢業或工作經驗一年以下者)

Key responsibilities for the role include: • Design of high-performance wireline and analog circuits • Develop power, performance, and area optimal topologies • Co-work with layout, digital, and system teams for optimal design • Discussions and presentations with clients Qualifications: • Minimum of a Masters or PhD in Electrical Engineering • Deep knowledge and experience designing a subset of SerDes building blocks: ADC, DAC, LC-Oscillators, PLL, CDR, CTLE, DFE • High-speed circuit design (>10GS/s) experience a significant asset • Multiple designs taped out, ideally in wireline projects • Experience working with Cadence tool flow • Experience with circuit layout and floor planning • Matlab/Simulink, Python experience • Comfortable with scripting and programming • Excellent communication and presentation skills • Strong team player 歡迎身心障礙者應徵