Principle Engineer - Packaging (FPGA)

09/09更新
6 小時前處理過履歷
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應徵

工作內容

We are seeking a highly motivated and experienced Principal Packaging Engineer to join our NPI Packaging team. You will be a member of the FPGA (Field Programmable Gate Array) Business Unit, which is a leader in research, development, and manufacturing of highly reliable non-volatile Field Programmable Gate Arrays. In this role, the candidate will be responsible for advanced semiconductor package development. The ideal candidate will have a background in semiconductor packaging and assembly, and a strong ability to collaborate cross-functionally, solve technical problems, and manage projects. Responsibilities: • Co-design packages with Silicon, Packaging, and Systems engineering teams to ensure designed packages meet electrical, mechanical and thermal requirements of high-performance flip chip packages. • Work with business unit’s IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new FPGA devices, satisfying business unit’s roadmap for new products. • Learn and define assembly BOM, process, troubleshoot, and support packaging issues of new advanced technology. • Create package design documentation and assembly instructions. • Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new technology/structure development etc.) • Manage package qualification for commercial and automotive applications. • Coordinate with assembly vendors on new packages from development to high volume production.

工作待遇

待遇面議

(經常性薪資達 4 萬元或以上)

工作性質

全職

上班地點

新竹市工業東四路24之2號6樓

管理責任

不需負擔管理責任

出差外派

無需出差外派

上班時段

日班

休假制度

依公司規定

可上班日

不限

需求人數

1人

條件要求

工作經歷

10年以上

學歷要求

大學、碩士

科系要求

電機電子工程相關、機械工程相關、材料工程相關

語文條件

英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通

擅長工具

不拘

工作技能

不拘

其他條件

• Bachelor's or Master's Degree in Electrical or Mechanical Engineering. • Minimum of 10 years of professional experience, including at least 5 years focused on semiconductor IC packaging. • Well versed with mid-range pin count packaging solutions, including but not limited to organic and ceramic flip chip BGA/LGA,WLCSP, wire bond BGA, and CSP. • Strong understanding of materials as related to chip packaging interaction. • Familiar with wafer BEOL (top metal, passivation, UBM, bumping etc.). • Strong knowledge of advanced substrate manufacturing/process.

福利制度

法定項目

其他福利

-年度特休假優於勞基法 -全額補助團保(員工本人、配偶及子女) -年度健康檢查補助 -婚喪喜慶及生育補助、三節禮金、生日禮金 -著重國際人才培訓,提供教育訓練方案,外訓課程補助 -Wellness Program

聯絡方式

聯絡人

陳小姐

其他

Any interested parties, please attach your resume in English.
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