Sr. Manager, Advanced Wafer Level Package (WLP) - (新竹)

We are seeking a highly experienced Senior Manager to lead the development of advanced wafer-level packaging (WLP) technologies, including heterogeneous integration, 2.5D/3D packaging, chiplet integration, and high-density interconnect solutions. The candidate will play a critical role in driving technology roadmaps, cross-functional R&D programs, and partner engagements to accelerate the deployment of next-generation semiconductor packaging solution What You Will Do In Your Role Technology Development & Roadmap - Lead the research, development, and implementation of advanced wafer-level packaging technologies (e.g., TSV, RDL-first/last, hybrid bonding, 2.5D/3D integration, fan-out, Si interposers, CoWoS, InFO, etc.). - Define and execute packaging technology roadmaps aligned with corporate strategy and market trends. - Evaluate emerging technologies, materials, and processes for feasibility and scalability. Package platform development for new product roadmap - Cooperate with global cross-functional R&D teams and external partners on developing package platform with good sustainability, manufacturability, reliability and decent performance. - Oversee prototype development, process qualification, and technology transfer to high-volume manufacturing. - Ensure projects meet technical milestones, schedule, cost targets, and yield goals. Ecosystem Engagement - Collaborate with foundry, OSAT, substrate, EDA, and materials suppliers to strengthen ecosystem partnerships. Team & People Development - Build, mentor, and lead a high-performance wafer level packaging R&D team. - Foster innovation, collaboration, and continuous improvement within the organization. - Support talent development and succession planning in the advanced packaging domain. The Experience You Will Bring Requirements: EDUCATION: REQUIRED: Master’s or PhD in Materials Science, Electrical Engineering, Mechanical Engineering, Applied Physics, or related field. WORK EXPERIENCE: REQUIRED: 1. 8+ years of relevant experience in advanced semiconductor packaging R&D, with at least 3 ~5 years in leadership/management roles. 2. Proven track record in wafer-level packaging, 2.5D/3D integration, or heterogeneous integration technology development. What Will Put You Ahead: - Hands-on experience with hybrid bonding, TSV, micro-bumps, fan-out, or chiplet architectures. - Strong knowledge in materials, process integration, thermal/mechanical reliability, and yield optimization. - Experience working with foundry/OSATs and driving technology transfer to HVM. - Excellent leadership, program management, and cross-functional collaboration skills. - Strong communication skills in English (verbal and written); Mandarin proficiency is a plus. - Experience with EDA tools for package co-design (electrical/thermal/mechanical simulation) preferred. At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate's knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy. Who We Are At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company. Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results.