Engineer, Advanced Wafer Level Package (新竹)

Your Job As an Advanced Wafer Level Package (WLP) Engineer, you will lead the development of cutting-edge wafer-level packaging technologies. Your role encompasses pioneering heterogeneous integration, 2.5D/3D packaging, chiplet integration, and high-density interconnect solutions. You will develop and validate advanced packaging processes such as RDL, TSV, Hybrid Bonding, Micro-bump, and Fan-Out. Additionally, you will perform material characterization, analyze packaging structures, resolve reliability issues, and collaborate closely across functions to ensure successful technology implementation and prototype development. Our Team You will be part of the DSS Division, within the R&D Component Engineering department, working closely with the Advanced WLP Senior Manager and cross-functional teams including design, integration, testing, reliability, as well as external partners such as material, equipment, and substrate suppliers. Our team is dedicated to pushing the boundaries of semiconductor packaging technology through innovation and collaboration. What You Will Do - Develop and validate advanced wafer-level packaging processes including RDL, TSV, Hybrid Bonding, Micro-bump, and Fan-Out. - Execute the development of heterogenous integration, 2.5D/3D packaging, chiplet integration, and high-density interconnect (HDI) solutions. - Conduct comprehensive material characterization and analyze packaging structures to identify opportunities for process optimization. - Define process parameters and establish design specifications to ensure manufacturability and high yield. - Support the introduction of new technologies and prototype sample development. - Perform failure analysis (FA) and address reliability issues to enhance product performance. - Collaborate cross-functionally with design, integration, testing, and reliability teams to ensure seamless project execution. - Liaise with material, equipment, and substrate suppliers to evaluate the feasibility and integration of new technologies. Who You Are (Basic Qualifications) - Master's degree or higher in Electrical Engineering, Materials Science, Mechanical Engineering, Physics, Chemical Engineering, Optoelectronics, or related fields. - Minimum of 2 years' experience in semiconductor packaging or process development. - Proficient in at least one of the following areas: RDL/Fan-Out process technology, TSV/Micro-bump/Hybrid bonding, Si interposer/CoWoS/InFO/3D IC, or material and structural reliability (thermal, mechanical, electrical). - Strong problem-solving skills and ability to collaborate effectively across functions. - Proficiency in reading and understanding English technical documents. What Will Put You Ahead (Preferred Qualifications) - Experience in wafer-level or advanced packaging technologies. - Hands-on experience in failure analysis (FA) and reliability testing. - Practical experience with wafer fabrication or back-end process operations. - Up-to-date knowledge of industry trends in advanced packaging technologies.