Digitial IC Design Verification Engineer

Familiar with digital IC design verification flow is a plus. Familiar with SV/UVM is a plus. Familiar with PCIE/NVMe is a plus. You will be in charge of making testplan according to the specification. You will take participate in creating verification testbench, test writing/debugging, and regression convergence. We focus on the storage related IP and prospective features. We provide high flexibility with days off and competitive salary.