IC Layout Engineer_HPI

Key Responsibilities: 1. Design complex layout for mixed signal and analog circuit in CMOS technologies. 2. Work with circuit designers to floor plan and complete the layout. 3. Run and fix complete set of physical design verification and reliability verification. 4. Review and analyze the layout with the circuit designers. 5. Layout integration and final verification for tape out. Qualifications: 1. Experience in 28nm process node is preferable. 2. 3 years of relevant analog mixed signal or Serdes layout design experience. 3. Experience in whole chip layout floor planning & integration. 4. Experience working with most EDA tools like Virtuoso layout editor(IC618)、 Calibre DRC/LVS/XRC、Laker OA or L3. 5. Must have strong communication skills and be a team player.