Senior Manager Design Verification

Bachelor's/Master's/Phd Degree in EEE/Computer/IC design 15+ YoE in Design Verification. Familiar with developing a DV plan based on Functional Specification, building the necessary test bench/infrastructure, developing tests, and verifying design. Familiar with UVM, SVA, Coverage Analysis. Formal Verification is a plus Senior Manager Design Verification Familiar with linux language: Verilog, System Verilog, Perl, C, Bash script, Python Familiar with UNIT (IP) and SYSTEM (Chip) level Verification. Familiar with AMBA bus and peripheral controller(for example DMA ...) Knowledge of Processor, ARM, CPU, PCIE, ETHERNET, DDR, USB is a plus Fluent in English; Taiwanese Mandarin is an advantage. Strong leader skill, manage one team with 5 member or above, well organized, methodical, and detail oriented