Senior Design Verification Engineer

Bachelor's Degree in EEE/Computer/IC design. 5+ YoE in Design Verification. Understanding the DV flow, create testplan, building the necessary test bench/infrastructure, developing tests, and verifying design. Experienced in UVM, SVA, Coverage Analysis. Functional Coverage is a plus. Experienced in Synopsys/Cadence Simulator and debugging flow. Familiar with Verilog, System Verilog. Familiar with linux language: C-shell, Bash script. Perl and Python is a plus. Experienced in UNIT (IP) verification. Knowledge of SYSTEM (Chip) level Verification is a plus. Knowledge of AMBA bus and peripheral controllers (for example DMA ...). Strong English communication skill. Quick to learn new technology.