Design Verification Engineer

PhD/Master in Degree in EEE/Computer/IC design. 1-3 YoE in Design Verification. Knowledge of the DV flow, update testlist, build test case. Knowledge of using Synopsys/Cadence Simulator and debugging flow. Understanding in Verilog, System Verilog. Understanding in linux language: C-shell, Bash script. Perl and Python is a plus. Knowledge of UNIT (IP) verification. Knowledge of AMBA bus and peripheral controllers (for example DMA ...). Knowledge of UVM, SVA, Coverage Analysis is a plus. Strong Taiwanese Mandarin communication; English proficiency is a plus. Quick to learn new technology.