The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.
【Key Responsibilities】
- Responsible for front-end digital logic design in ASIC/SOC projects.
- Perform HDL coding (Verilog/SystemVerilog).
- Prepare and maintain design documentation (specifications and design documents).
- Conduct RTL quality checks (Lint, CDC, power analysis, etc.).
- Collaborate with Backend/Physical Design engineers to achieve timing closure.
【Core Requirements】
- Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience.
- RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL.
- TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA.
- EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis).
- Documentation: Ability to write design specifications and technical documents.
- Collaboration: Work closely with the Design Verification (DV) team on IP verification.
【Preferred Qualifications】
- Familiarity with CPU architectures (x86/ARM/8051).
- Knowledge of AMBA bus protocols (AXI/AHB/APB).
- Understanding of PCIe protocol.digital IP/SOC design verification.
This is a good opportunity to join a startup company working in UWB and Radar product.
Co-work with ASIC design team for product development
competive salary and startup package
工作內容:
- 協助 Radar 定位演算法DSP實現及其驗證
- 協助數位晶片Serial介面(I2C/SPI)開發
- 協助產品驅動程式開發和相關測試
具備條件:
- 具3年以上Digital IC design或FPGA開發相關經驗
- 熟悉RTL coding、simulation & synthesis流程及其開發工具使用
- 具C/C++ coding 和 debug 能力
- 能理解基礎數位運算原理如FIR IIR cordic佳
Job Description:
Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.
Key Responsibilities:
• Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality.
• Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device.
• Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise.
• Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered.
• Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.
【產品線描述】
1. AMOLED, AR, VR, TDDI等面板驅動IC與觸控IC設計
2. 頂級系統廠ASIC產品合作開發
【工作說明】
1. 高速介面設計
2. 記憶體控制單元設計
3. 面板時序電路設計
4. 面板顯示優化控制單元設計
【必要條件】
1. MS degree in EE fields
2. Good at digital IC front-end design flow such as Verilog RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA
3. Must be a good team player with strong desire to succeed.
• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality.
• Co-work with SOC team to complete Bump floorplan and RDL routing.
• Power mesh/power density flow development and related flow development and enhancement.
• Provide power plan result for PR team.
• Chip IR signoff : provide the result and solution to APR & package team
• Chip level PEM/SEM simulation and fixing plan providing.
• SIR/DIR/PEM/SEM result data review and verification.
• Familiar with Voltus / Redhawk experience is required.
1. Project execution: DFT structure design and test pattern generation
2. Flow support: DFT flow enhancement and automation
3. ATPG related task and chip debugging support
Responsibilities:
• Develop integrated verification environment.
• Verify designs with system verilog and system verilog assertion.
• Build, maintain and upgrade testbenches and their components using UVM-based methods.
• Check functional coverage and code coverage
• Create controlled random testcases. Pre-debug and provide debug reports.
• Scripting experience using scripting languages like Perl and Python.