「Multimedia SoC IC數位電路設計 資深工程師/主管」的相似工作

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

1. Integrate and modify USB2.0 controller IP 2. Solve issues and plan CP/FT of USB projects 3. Design and verify digital circuits.

1.負責影像處理設計及架構 2.了解ASIC Flow及獨立作業 3.能擔任專案負責人

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

數位IC設計

我們專注於打造次世代電路模擬專用硬體加速器，誠徵SoC系統架構工程師，加入我們的行列，透過系統整合驅動硬體創新，徹底改寫電路模擬及分析解決方案的效能與整合度天花板。 你將負責： 設計SoC系統架構和功能分割，定義數位與類比功能區塊 開發SoC內部互連架構和資料流路徑最佳化方案 協調數位IC和類比IC的功能整合與系統驗證 建立SoC設計流程並進行系統效能與功耗優化 我們期待你具備： 碩士以上學歷，熟悉完整SoC設計流程（規格→架構→實現→驗證） 精通SoC系統架構設計（CPU/DSP、記憶體階層、匯流排架構、電源管理） 熟悉RTL設計、SystemVerilog/VHDL與SoC驗證方法學（UVM等） 具備SystemC、MATLAB/Simulink系統建模與EDA工具鏈操作能力 加分條件： 有電力電子、電源管理或混合信號SoC整合經驗 熟悉DSP或專用處理器架構設計 具備先進製程節點（28nm以下）設計考量經驗 有成功的SoC tapeout和量產經驗 如果你熱愛用系統整合重新定義電力分析晶片的可能性，歡迎加入我們，打造更智慧的硬體未來！

1. Driver IC 設計 2. TCON IC 設計 3. 高速介面電路設計 4. 依照演算法開發設計數位電路，以達到系統的要求。

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

We are seeking a highly motivated Digital IC Design Engineer to join our dynamic team. The ideal candidate will have a strong background in digital design, a passion for innovation, and the ability to work collaboratively in a fast-paced environment. 1.Design and implement digital integrated circuits for low power MCU, including timing control, image processing, GPIO, and interface control. 2.Collaborate with cross-functional teams to define specifications and requirements. 3.Perform RTL design using VHDL/Verilog and simulation using tools such as ModelSim or VCS. 4.Conduct functional verification and validation of designs through simulation and formal methods. 5.Develop low power image processing and camera control algorithms, pipelines, and HW-friendly imaging technologies. 6.Hand on ISP block (AE, AWB, BPC, etc.) design and modification. 7.Optimize designs for performance, area, and power consumption. 8.Participate in design reviews and provide constructive feedback. 9.Assist in the integration and testing of digital systems. 10.Review technical literature, collect data, and specify solution options. Design, analyze, simulate, test, and document algorithm options. 11.Familiar with MIPI, I2C, serial, parallel output data control is plus. 12.Familiar with design flow and block integration is plus. (Required for manager) 13.Participate in system requirements definitions and schedule plan. ( Required for manager). Preferred Qualifications: 1.Experience with low-power design techniques. 2.Knowledge of hardware description languages and electronic design automation (EDA) tools. 3.Familiarity with mixed-signal design concepts is a plus.

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Ethernet SerDes高速介面數位設計 (USXGMII, 25G Base-R) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL), 和軟體同仁合作進行相關驗證 3. 具有高速介面或 high level synthesis實作經驗或FPGA實作經驗者尤佳

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469791 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469791 【The Potential Areas To Work】 The main responsibility of this position is to do the performance verification for world-class custom CPU for mobile and portable computers. 【Roles and Responsibilities】 -Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc. -Verify performance feature between RTL and model, and have ability to troubleshooting -Work with design team and performance team to develop test case and validate new feature

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow