「FPGA資深/主任工程師_5G(台北/新竹)」的相似工作

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

(1) FPGA軟硬體開發 (2) Verilog程式開發 (3) 軟硬體除錯

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

ᴘᴜʀᴘᴏsᴇ ᴏғ ᴛʜɪs ᴘᴏsɪᴛɪᴏɴ 運用 FPGA 技術打造高效能與高可靠性的工業網路產品，支援全球製造、能源與交通等關鍵產業的數位化轉型。 ᴍᴀᴊᴏʀ ᴀʀᴇᴀs ᴏғ ʀᴇsᴘᴏɴsɪʙɪʟɪᴛʏ 1. 負責 FPGA 邏輯設計、Simulation、驗證與 Debug。 2. 與 EE、FW、PM 等跨部門協作，確保系統整合穩定，及時回應客戶需求。 3. 維護既有產品並持續改善品質與效能。 4. 撰寫設計與測試文件，遵循並優化開發流程。 5. 協助新產品平台架構設計與技術評估。

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

A. 負責高階投影機FPGA開發 B. 承接 FPGA (XILINX/ALTERA) 設計 C. 數位電路設計、驗證與模擬 D. 影像系統或數位影像處理演算法設計與實現

The Team and Role: The Embedded SW Test team’s mission is to strengthen the firmware validation process and fully automate the test procedures. We develop truly innovative test instruments and tools to achieve this goal. The FPGA Firmware Developer /Test Engineer is responsible for designing, implementing and testing FPGA firmware used for test automation. Your Contribution: Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will: • Participate in the development of a test automation framework • Leverage your technical hardware and software skills to design & implement the testing infrastructure • Evaluate and develop new FPGA modules to automate the integration test suites for our next generation devices • Develop, run and maintain automated scripts to prove product conformity regarding component specification • Improve processes or propose improvement where’s applicable

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

1. Work closely with Hardware, BIOS ,BMC, and Firmware team for CPLD / FPGA design, validation, and maintenance. 2. Develop multiple bus protocols including I2C / power sequence / SPI / LPC / SGPIO / I2C switch/ UART / PWM / eSPI on Server / Storage product by CPLD/FPGA. 3. The test issue analysis and track and troubleshoot of the project.

產品領域: 影像, CPO及衛星光通訊產品使用之 FPGA。 工作內容: 1. 熟練使用Verilog及VHDL 2. 熟悉Combine/Sequential Logic、FSM、pipeline、clock domain crossing (CDC)、reset strategy 等應用 3. 自動化設備嵌入式系統開發 4. 研發設計FPGA-Based Video/Camera 應用 5. 熟悉FPGA系統開發、RTL Coding、Altera Quartus II或Xilinx Vivado 6. 協助驗證FPGA電路(Schematic) 7. 具備基礎MS Windows Programming能力者佳 8. 熟悉I2C、UART、I2S 等protocol 者佳

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

DDC (Digital Design Center, 數位設計中心) 成立於2021年，配合集團在智能製造、工業4.0的發展，主要致力於將台達集團內部的【CAD設計相關之工程資訊】，標準化、結構化、數位化來加速實踐智能製造。持續依照三個目標進行，(1) 協助建立跨事業單位的 CAD 工程設計準則，建立一致性、通用性的規範；(2) 建立 CAD 零件標準化軟體，整合跨系統之間的 CAD 資訊串聯；(3) 建立 CAD 系統自動優化與調適，以實踐 Closed-Loop 智能製造。 【工作內容】 1. 基於電路設計工具進行相關檔案解析與萃取 2. 自動化控制 MCAD/ECAD/CAE 工具等相關研究與設計 3. 3D STP 檔相關解析與應用研究 4. 演算法設計與開發 【具備技能】 1. 熟悉 Python 程式語言 2. 至少熟悉一套 MCAD/ECAD/CAE 領域工具，如AD/ Allegro/ OrCAD/ Creo/Maxwell等 3. 邏輯清晰並具研究精神以追蹤並解決問題 4 創新精進能力，持續學習進步

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

按讚並追蹤"台達Delta Career"FB粉絲專頁，讓您更快掌握台達職缺脈動！ https://www.facebook.com/deltacareer 想知道電子設計工程師的一天嗎? 給我三分鐘，讓你一窺台達EE的一天 影片傳送門在此:： https://www.youtube.com/watch?v=b33Lrotur1w 產品別：個人電腦攜帶式電源 1. 執行並協助新技術/新資訊引進與構思 2. 協助問題分析與追蹤、工程樣品製作與工程/設計變更評估 3. 執行零件材料選用及供應商導入 4. AC/DC、DC/AC、DC/DC拓樸應用與設計 5. 輔助電源、電路信號採樣電路與保護電路設計與分析 6. 協助市場產品趨勢研究 7. 執行電路理論分析驗證 8. 電路建模與模擬分析驗證 9. 電路設計最佳化 10. 執行專案進度管理