【工作內容】
• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market
• Provide the technical leadership to the DV team for the project
• Work independently on various DV tasks and provide technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
【職務條件】
• Master’s degree in Electrical Engineering, Computer Science, or related.
• Good understanding of ASIC design verification flow.
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences.
• Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
【其他條件】
• MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification
• MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.
1. Participate in digital design specification, architecture definition, and microarchitecture planning.
2. Conduct FPGA prototyping, testing, and debugging of digital IP designs.
3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration.
4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.
Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets.
1. 研讀規格。
2. IC數位邏輯線線路的研發設計。
3. IC數位邏輯線路模擬與合成。
4. FPGA的合成規劃與測試驗證。
5. IC的靜態時序分析 (Static Timing Analysis)。
6. IC佈局後的線路模擬。
7. 撰寫IC規格設計書。
8. IC的除錯與工程變更修改。
9. 協助系統應用部門的進行IC驗證版的規劃。
Overview
We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration.
Key Responsibilities
Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI).
Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction.
Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs.
Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput.
Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines.
Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.