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Job Mission
Represent manufacturing and act as gatekeeper from manufacturing to D&E function
Add value in overall manufacturing processes such as forming, machining, joining, and assembling
Job Description
Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat
Identify gaps and drive assigned process improvement projects and successful delivery
Initiate and drive new procedure changes and projects
Develop and maintain networks across several functional stakeholders
Prioritize works and projects based on business situation
Transfer knowledge and train colleagues on existing and newly introduced products
Education
Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics)
Experience
3-5 years working experience in design engineering
Personal skills
Show responsibility for the result of work
Show proactive attitude and willing to take initiative
Drive for continuous improvement
Able to think outside of standard processes
Able to work independently
Able to co-work with different functional stakeholders
Able to demonstrate leadership skills
Able to work in a multi-disciplinary team within a high tech(proto) environment
Able to think and act within general policies across department levels
Diversity and inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
Need to know more about applying for a job at ASML? Read our frequently asked questions.
1. 負責數位IC設計整合:
a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格
b. 完成SoC系統架構設計,並依功能單元運作屬性區分區塊規格
c. 使用Verilog/VHDL編程內部功能並撰寫RTL code
2. 負責功能驗證與除錯
a. 制定功能驗證計畫
b. 審核驗證計畫的完整性和正確性
c. 進行基本模擬,確認RTL code的功能
d. RTL code寫入FPGA晶片連接系統測試,驗證RTL code
3. 負責時序分析與功耗管理
a. 產出邏輯閘級電路連線網表(netlist)
b. 進行SoC系統的時序分析
c. 進行SoC系統的功耗分析
4. 其它主管交辦事項
【必要條件】
1. 電機、電子、資訊工程或相關科系,碩士以上學歷
2. 三年以上 SoC 設計或整合經驗
3. 熟悉CPU子系統設計整合
a. 熟悉 ARM 架構,
b. 對 RISC-V 架構有基本認識
4. 熟悉數位IC前端設計流程,如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等
5. 具類比IP整合相關經驗,例如PHY、Serdes、PLL等
6. 熟悉IC後段設計流程,如DFT、MBIST、P&R、post-cilicon system level debugging等
[job description]
Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard.
You will also contribute to design concept discussion, architecture definition, as well as design implementation.
‧ Architecture design and RTL implementation
‧ System bus and related peripheral designs
‧ SoC and emulation platform design
‧ SoC system performance analysis
[Requirement]
1. Bachelor's or Master's degree in Electrical Engineering or related fields
2. Familiar with RTL design, SystemVerilog, front-end design flow
3. The following working knowledge is desired:
* Python programming
* TCL scripting
* Universal Verification Methodology (UVM)
* Low power design and analysis
Responsibilities:
• Develop integrated verification environment.
• Verify designs with system verilog and system verilog assertion.
• Build, maintain and upgrade testbenches and their components using UVM-based methods.
• Check functional coverage and code coverage
• Create controlled random testcases. Pre-debug and provide debug reports.
• Scripting experience using scripting languages like Perl and Python.