「元件工程師(SPICE Modeling)(內湖)」的相似工作

1. Device characterization and test key design. 2. 元件量測並提供desinger相關規格數據 3. 記憶體陣列設計

製程整合/元件開發

Overview: The Senior TCAD Engineer will be a key member of our technology development team, responsible for advanced modeling and simulation of semiconductor devices and fabrication processes. This role involves defining and executing TCAD projects for novel device architectures, optimizing performance, and analyzing results to guide process integration and design teams. Key Responsibilities: • Develop and validate TCAD models for advanced technology nodes. • Run simulations to assess device performance (IV, CV, breakdown, reliability). • Interpret results to guide design and process improvements. • Collaborate with engineering teams to align on technology roadmap. • Act as TCAD expert and provide technical support. • Automate simulation tasks using scripting (Python, Perl, TCL). • Compare simulations with silicon data and resolve discrepancies. • Prepare technical reports and present to cross-functional teams. • Stay updated on TCAD trends and enhance modeling capabilities. • Mentor junior engineers and contribute to IP development. Qualifications: • 5+ years of hands-on experience in TCAD process and device simulation within the semiconductor industry. • Deep understanding of semiconductor device physics and fabrication processes. • Expertise with commercial TCAD simulation tools such as Synopsys Sentaurus or Silvaco Atlas. • Proficiency in scripting languages (e.g., Python, Perl, TCL) for tool automation. • Experience with analog focused process technologies, particularly high voltage transistors such as drain extended CMOS or LDMOS devices.

Overview: MOSFET Design Team offers the innovative environment for talents to dive deep into the world of device design, platform development, and research. We offer working locations in both Xindian and Tainan. Come and join us to focus on the most cutting-edge semiconductor materials and applications! Key Responsibilities: • Develop and execute innovative device layouts in line with customer requirements, ensuring optimal functionality and efficiency. • Partner with PE and Quality teams to enhance device reliability and address any arising issues in time. • Establish and continuously optimize SPICE models to reflect the characteristics of both new and existing devices. • Work alongside the PIE team and collaborate with external foundries, paving the way for the next generation of advanced devices. • Drive the research and patenting efforts centered around novel designs, applications, and advanced materials, such as GaN and SiC. • Accomplish additional tasks delegated by the supervisor. Qualifications: • A Master’s degree in EE, Physics, or a related field. • Expertise in power devices, with a spotlight on UMOS, SGT, LDMOS, MLSJ, GaN and SiC. • Comprehensive understanding of device physics and semiconductor manufacturing processes. • Proficiency in semiconductor simulation tools. • Strong English communication skills, catering to both technical and non-technical stakeholders.

Tcad模擬、元件量測與分析

1.ESD/TVS保護元件設計 2.積體電路系統級ESD防護設計 3.等主管交辦事項

※實際任用職稱依個人相關經歷敘薪。 1.新產品開發生產規劃及工程驗證 2.晶圓廠製程開發及元件競爭力評估導入 3.工程/量產低良分析及良率改善 4.協助客訴品電性/物性分析

Overview: This role is responsible for leading new product initiatives, crafting detailed datasheets, and fostering cross-departmental collaboration. The ideal candidate possesses a deep understanding of IC/MOSFET fabrication, semiconductor testing, and is adept at navigating Power industry nuances. Strong communication skills and self-motivation are paramount. Key Responsibilities: • Steer new product development processes, ensuring timely releases and meticulous schedule management. • Craft and disseminate product datasheets to maintain clarity and accuracy. • Provide steadfast support for Sales & Marketing teams in design-in activities, bridging technical knowledge with market needs. • Oversee product life cycles, encompassing EOL, ECR, and PCN in alignment with product roadmaps and BU strategies. • Ensure production-embedded changes through systematic controls and participate in SCS part creations. • Engage actively with multifunctional teams, crossing from Sales & Marketing, Design, and Quality, to address challenges in fabrication, packaging, testing, and application. • Accomplish additional tasks delegated by the supervisor. Qualifications: • Comprehensive knowledge of semiconductor testing, assembly, and IC/MOSFET wafer fabrication processes. • A strong foundation in electronic analysis. • Exceptional communication and negotiation skills. • A self-starter mindset with readiness for individual contributions. • Experience in the Power industry is a plus.

* OSAT (Assembly/Test) 良率異常分析 & 處理。 量產測試驗證，確保量測參數 & 規格符合設計要求。 * 測試結果資料分析，提供良率改善 & 測試流程優化建議。 * CP / FT / SLT 數據追蹤，擬定調整製程參數 or 條件。 測試開發、Debug & 參數優化，提升測試效率 & 良率穩定度。 * 與內部製程/設備/品保單位進行問題分析，釐清異常並提出改善方案。 * 支援測試需求 & 技術交流，確保產品測試時程 & 品質達成量產目標。 1. Co-work w/ functional engineering team member (TME/DE/TD/TE/RE) to make new product has good definition, Risk evaluation and Build comprehensive testing plan / Qual plan, etc. 2. Co-work w/ other Engineering team member to ensure all new product can be thoroughly Manufactured, Characterized and Qualified for reliabilities and qualities. 3. Organize assignments and independently schedules to complete assigned tasks timely and make project finished efficiently. 4. Have good Coordination and Data Analysis to solve difficult problems through application of various techniques and approaches to develop effective and practical solutions that result in improved products, processes with good quality. 5. Co-work with MediaTek - Taiwan Team, and HCLTech - India Team. 6. Annual salary: 800K NTD and above 7. Onsite MediaTek - Hsinchu Science Park Office This position is set for PE (Product Engineer) to coordinate new product development activities, ensure timely completion of all new products manufacturing, testing, characterization, qualification and releasing with good consistency, quality and efficiency. Ref. * CP (Wafer level - Chip Probing) * FT (Packaged chip level - Final Test) * SLT (Packaged chip level - System Level Test) * ATE (Automated Test Equipment)

工作概覽： 參與CMOS平台製程開發、元件設計與電性優化，支持新產品導入、製程整合與技術創新，為特殊應用產品提供完整的製程與元件解決方案。 主要職責： • 負責0.35um CMOS製程模組與整合開發。 • 參與元件(如MOS、HVLDMOS、電容、電阻等)之設計與TCAD模擬驗證。 • 建立元件模型(SPICE/LPE) 與電性分析，協助PDK開發。 • 協同設計團隊進行元件規格定義與效能驗證。 • 支援新產品導入、製程異常分析與良率改善。 資格條件: • 熟悉0.35um CMOS製程平台。 • 具元件設計、TCAD模擬或SPICE建模經驗者尤佳。 • 具備製程整合、電性量測與數據分析能力。

1. 產品電子電路設計並提供開發方向建議 2. 產品應用方案與應用電路設計(EVB、Demo Board) 3. 產品驗證平台開發與電路設計(特殊產品特性測試電路、可靠性驗證電路) 4. PCB 電路Layout佈局 5. 磁性元件設計 6. 電路模擬(Simetrix/Simplis or PSPICE or Others) 7. 撰寫產品Application Note 8. 協助蒐集與分析產品市場應用趨勢 9. 協助客戶教育訓練 10. 協助產品品質事件分析 11. 協助新客戶與新應用市場開發

1. 數位、類比信號PI/SI模擬及設計優化。 2. VNA、TDR、oscilloscope儀器量測及操作 。 3. 其他主管交辦事項。

請務必投遞官網(12475): https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-staff-engineer/44408/85440860528 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

1. 產品電性量測分析與測試報告產出 (MOSFET、DC-DC IC、AC-DC IC) 2. 產品規格書製作 3. 新產品單體與系統驗證 4. 協助客戶問題回覆(需跨部門合作以及客戶溝通)

【本職缺可透過104應徵，也歡迎直接至穩懋官方網站投遞，增加履歷曝光度】請至穩懋官方網站投遞個人履歷表，此職缺履歷登錄網址：https://www.winfoundry.com/WinTalentPool/JobRequirement/Edit/14 1. Perform DC/RF characterization, analysis, and modeling of semiconductor devices, including GaN, HBT, pHEMT, switches, diodes, and passive components. 2. Develop EM substrates for ADS and Microwave Office (MWO) simulation tools. 3. Operate measurement equipment such as probe stations, network analyzers (PNA), and DC power supplies. 4. Support design kit development and release.

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4mmbZ92 [工作內容] 1. Develop and maintain DRC related Calibre SVRF/TVF rule deck and tech file. 2. Develop and maintain dummy-fill utility to enlarge margin of processes. 3. Support designer/layout to fix design rule related issue. 4. Maintain Laker GUI for layout users. 5. Build and optimize automation flows (Python/TCL/Perl).

1. 專案開發前期: 協同SA訂定規格/設計環境建構/競品特性分析/協同PM訂定開發時程表 2. 專案開發期間: 支援電路設計及整合/定期招開設計檢查會議/定期追蹤開發進度/確保專案各站點完成時程/準備各站點檢查資料及文件/測試相關資料的準備 3. 專案開發後期: 分析CP驗證數據/確保良率達標/協同SA,RD,TE進行除錯分析/確保達送樣標準

1. 協助業務處理客戶對產品相關應用問題的技術諮詢及售後服務。 2. 客戶端產品初判、覆判與資訊收集與管理。 3. 撰寫產品說明書和技術文件。 4. 協助產品測試和問題回饋。 5. 客戶專案議題之內部整合與追蹤。 6. 其他主管交辦之工作事項。 7. 跨部門溝通協調。 本職位旨在協助業務處理客戶對產品相關應用問題的技術諮詢及售後服務，提供客戶端產品初判、覆判與資訊收集與管理。此職位作為公司業務與客戶之間的重要溝通橋樑，具有開發前景。 歡迎有志之士加入我們的團隊，成就自己的事業！有意者請提供履歷表。

先進SRAM 設計及開發

【工作內容】 1. 熟悉2.5D/3D架構，如CoWoS、WoW等技術家族。 2. 具備WoW hybrid bonding技術，能支援開發與量產。 3. 執行電性失效分析（EFA）與產品參數規格特性分析，協助問題釐清與品質提升。 【職務需求】 1. 3年以上製程整合相關經驗，熟悉2.5D, 3DIC, Hybrid Bonding優先。 2. 熟悉半導體DRAM製程技術，包括光罩設計、蝕刻、CMP、鍵合。 3. 具備製程良率分析、故障排除與問題解決能力。 4. 熟悉跨部門溝通與專案管理，能有效協調多方資源。