「SoC設計驗證經理」的相似工作

我們專注於能源晶片與深度演算法的融合創新，誠徵SoC系統架構工程師，加入我們打造次世代電力分析專用SoC晶片的行列，透過系統整合驅動硬體創新，徹底改寫電力分析解決方案的效能與整合度天花板。 你將負責： 設計SoC系統架構和功能分割，定義數位與類比功能區塊 開發SoC內部互連架構和資料流路徑最佳化方案 協調數位IC和類比IC的功能整合與系統驗證 建立SoC設計流程並進行系統效能與功耗優化 我們期待你具備： 碩士以上學歷，熟悉完整SoC設計流程（規格→架構→實現→驗證） 精通SoC系統架構設計（CPU/DSP、記憶體階層、匯流排架構、電源管理） 熟悉RTL設計、SystemVerilog/VHDL與SoC驗證方法學（UVM等） 具備SystemC、MATLAB/Simulink系統建模與EDA工具鏈操作能力 加分條件： 有電力電子、電源管理或混合信號SoC整合經驗 熟悉DSP或專用處理器架構設計 具備先進製程節點（28nm以下）設計考量經驗 有成功的SoC tapeout和量產經驗 如果你熱愛用系統整合重新定義電力分析晶片的可能性，歡迎加入我們，打造更智慧的硬體未來！

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a USB Software Engineer at Augentix, you will be responsible for implementing, validating, and productizing USB functionality on our next-generation SoCs. These SoCs feature USB 3.1 Gen1 (5Gbps) capability and are designed to support a wide range of USB applications including USB boot, DFU (Device Firmware Upgrade), UVC (USB Video Class), UAC (USB Audio Class), and MSC (USB mass storage class), and our proprietary high speed debug inferface. You are also responsible smooth host mode operations. [Responsibilities] ★ Own the design, development, and verification of USB functionalities from FPGA prototyping to real silicon bring-up. ★ Implement USB bootloader and DFU support in alignment with platform bring-up and secure boot strategy. ★ Develop and validate USB class drivers for UVC, UAC, and MSC in Linux. ★ Maintain smooth operations in host mode. ★ Debug USB protocol and electrical issues across PHY, Link, and Class layers. ★ Collaborate with architecture, board design, validation, and SDK teams to ensure robust integration. ★ Enable customer-facing SDK features and provide engineering support as needed. ★ Work with cross-functional teams to align Linux kernel integration and compliance testing. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Master's degree in Electrical Engineering, Computer Science, or related field with 3+ years of relevant experience, or a PhD in a related field. ★ Proficiency in C and embedded Linux kernel development. ★ Hands on experience in USB stack development and Linux kernel driver programming ★ Proficiency with USB 2.0/3.x protocols and USB controller/device frameworks under Linux ★ Familiar with embedded Linux bring-up, BSP development, and bootloaders (e.g., U-Boot) ★ Hands-on experience with oscilloscope, logic analyzer, or other low-level debug tools. ★ Ability to work across user space and kernel space boundaries. [Preferred Qualifications] ★ Experience enabling USB-related features in secure boot or recovery workflows ★ Knowledge of secure boot, fast boot and always-on-video (AOV) is a plus. ★ Understanding of USB compliance and certification processes ★ Experience with FPGA bring-up or post-silicon validation. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

UltraSense Systems, headquartered in Silicon Valley, is revolutionizing human-machine interfaces (HMI) through its cutting-edge SmartSurface technology. Our InPlane Sensing platform seamlessly integrates touch, lighting, and haptic feedback into everyday surfaces, delivering intuitive, responsive, and premium user experiences across automotive, consumer electronics, and other industries. Join our mission to create the next generation of smart, touch-sensitive surfaces that are both functional and aesthetically superior. Summary UltraSense Systems is seeking a creative Senior Engineer, Ultrasound Algorithm Development to help develop the prototype of a groundbreaking new product. In this role, you'll collaborate with a high-caliber team to design and build devices that break new ground in the industry. This role involves hands-on algorithm development, acoustic signal processing, and system development. Key Responsibilities ．Lead design, development, and prototyping of ultrasound sensor systems—from concept through testing and iteration (inspired by Xwave Innovations roles) ．Develop, implement, and optimize acoustic signal processing algorithms, including beamforming (phased array/delayandsum), synthetic aperture techniques, and advanced array processing ．Write clean, efficient, well-documented Python code for simulation, modeling, and real-time signal acquisition/processing ．Build and integrate prototype hardware and firmware components (e.g., piezoelectric transducer interfacing, digitizers, array electronics) ．Conduct simulations, modeling (e.g., FEA or acoustic propagation), and validation testing; iterate to improve system performance ．Analyze sensor data, benchmark performance metrics, debug acoustics chain (from raw signals to processed outputs), and refine algorithms and hardware　accordingly ．Collaborate with cross-functional teams—mechanical, electrical, software—to define system requirements and drive integrative design (common across R&D roles) Minimum Requirements ．Degree: M.S. or Ph.D. in Electrical Engineering, Acoustics, Computer Science, Applied Physics, or a related field ．Hands-on experience (3–5+ years) in acoustic/ultrasound signal processing or sensor systems, including beamforming and array processing (phased arrays, delay-and-sum, synthetic aperture, etc.) ．Strong proficiency in Python for algorithm development, data analysis, and simulation (e.g., with NumPy, SciPy, MATLAB not essential but a plus) ．Practical experience with prototyping hardware—working with transducers, pulser/receiver logic, data acquisition systems, or similar instrument interfacing ．Solid understanding of acoustic wave propagation, ultrasound physics, signal-to-noise enhancement techniques, and array signal processing principles ．Excellent communication, writing, and documentation skills; ability to draft technical reports, collaborate with teams, and present findings clearly (noted across industry postings) Desired Requirements ．Ph.D. in relevant field, with a proven R&D track record, including publications, patents, or conference papers ．Experience with FEA modeling or acoustic simulation tools, especially for transducer design or wave propagation analysis ．Background in device fabrication, CAD design, or microelectronic processing (e.g., GDS patterning) is a plus ．Familiarity with synthetic aperture ultrasound techniques or advanced imaging methods ．Experience developing adaptive or data-driven beamforming (e.g., deep learningenabled approaches for ultrasound) ．Proficiency in embedded platforms or real-time firmware, including porting signal processing algorithms into C/C++ or FPGA/ASIC environments ．Proven ability in small R&D environments—self-motivated, resourceful, and highly collaborative ．Comfortable working in a fast-paced, cross-functional environment ．Creative thinker with a passion for tackling unfamiliar challenges ．Eagerness to contribute to early-stage product innovation and development

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1.熟悉硬體工程師的職責。 2.design philosophy, circuit entry , layout guidance ,performance analysis, prototype debugging。 3在ARM based 領域，Linux platform。 4.對FPGA 熟悉，或RFSOC 清楚。

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

1. 負責設計前期之分析，設計概念發想，擬定產品開發策略。 2. 負責產品設計、開發進度與品質、成本的控制管理至成功試量產。 3. 負責研發單位作業流程優化、產品計畫與研發專案管理。 4. 帶領團隊執行研發計畫、精進產品技術，並達成各項效率指標。 5. 優化產品設計與協助生產單位建立基礎工程團隊以提升產品製程能力。 6. 整合機構、電控、軟體等功能性研發團隊，督導各項產品專案研發進度以支援產品線業務發展之產品需求。 本職位將負責產品設計開發，並帶領團隊完成研發計畫。此職位具有重要性，對公司未來發展具有影響力。

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

(1) 自動化設備運動控制晶片研發 (2) 熟悉FPGA系統開發、Altera Quartus II (3) 協助驗證控制晶片週邊電路(Schematic) (4) 具備基礎工業控制知識者佳

1) FPGA synthesis, verification, and env. maintain一年以上FPGA使用經驗 2) CP/PT pattern creation and chip validation 3) 熟CMOS原理&CCM設計 4) 懂基礎C/C++,基礎Linux. 5) 編寫技術文件 ,電路設計,IC 訊號測試&功能量測

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

1.研究、設計、模擬與驗證類比及NVM IC電路。

[Responsibilities] ★ Analyze and optimize SoC power and performance trade-offs at block and system level ★ Define and implement power management strategies across various IPs and subsystems ★ Work with architecture and design teams to evaluate new feature impact on power and performance ★ Develop use-case-driven workloads for pre-silicon power/performance analysis ★ Collaborate with verification and software teams for modeling and validation ★ Correlate pre-silicon analysis with post-silicon measurements to enhance model accuracy ★ Occasional business travel across APAC and other regions may be required [Minimum Qualifications] ★ Master's degree in Electrical Engineering or a related field with 5+ years of relevant experience, or a PhD in a related field. ★ 3–5 years of hands-on experience in SoC power/performance architecture or relevant chip design roles ★ Solid experience in low-power design techniques, such as DVFS, clock gating, and power retention ★ Familiarity with power analysis tools (e.g., PrimePower, PowerArtist, PT-PX) [Preferred Qualifications] ★ Strong understanding of SoC microarchitecture, including CPU, interconnect, and memory hierarchy ★ Proficient in scripting languages such as Python, Perl, Tcl, or Shell for automation and data processing ★ Comfortable working in a globally distributed, cross-disciplinary engineering team ★ Excellent problem-solving skills, with the ability to work independently and collaborate across teams ★ Experience with performance modeling or benchmarking is a plus ★ Exposure to post-silicon power/performance bring-up and correlation is a strong advantage

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

(1) 全面負責工程部的工作管理，含蓋內容：產品工程、製程工程、機構工程 (2) 負責製程資源整合和精實，掌握生產品質與效率提升 (3) 配合生產作業安排與異常處理回報 (4) 新製程開發 (5) 主導製程變更與改善會議 (6) 主導客戶定期工程相關會議 (7) 負責人員認知引導、紀律與知識技能提升

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4lHkbzD [工作內容] 1. Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization. 2. Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff. 3. Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability. 4. Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

Job Responsibilities: 1. Following R&D product design process to implement the hardware design. Ability to communicate clearly with team members and teamwork skills. 2. Cooperate with a cross-functional team of Engineers (EE, software, Thermal, mechanical, CAD, DFX, Test, etc.) and others in the development and support of new product introductions. 3. Serve as the senior technical advisor for the product line for the end-to-end life cycle of the product. Ensure operations technical readiness for all phases of the introduction cycle. 4. Identify, prioritize and manage key technical changes and risks of a given product; ensure all technical risks associated with a product are identified and closed or mitigated to enable the quality ramp of a product. 5. Review and submit all equipment requirement plans, along with an assessment of the robustness of the solution to meet the requirements of the operation, and the implementation of any additional solutions to mitigate any risks to the plan. 6. Deriving the functional specification and architecture for a subsystem or circuit pack based on system requirement. 7. Component selection/qualification; interacting with electrical/optical component vendors. 8. Documenting all technical design files. 9. Logic thinking and communication with customers Qualification: 1. A university degree in EE/CS, or a master’s degree is preferred. 2. With 8+ years relevant experience, preferable in communication product design and applications, such as datacenter switch, router, carrier switch, etc. 3. Experience with key switch silicon, such as Broadcom, Marvell, Cavium, etc. Experience in communication interface, such as XAUL/GMII/SGMII /XFI/PCI/PCI-E/ buses required 4. Knowledge on high-speed design, 25G SERDES is preferred 5. Experience in product testing, certification. 6. Excellent understanding of digital hardware design, power design, and high speed interfaces, timing analysis and signal integrity issues. 7. Understanding of analog electronic concepts and EMC. Can supervision of layout design. 8. Working knowledge of Concept schematics capture, Signal Integrity simulation, Verilog HDL, familiarity with Allegro. 9. Experience with high volume run products, test and verification of circuit packs designed. 10. Supporting new product introduction/transition to EMS. 11. Be familiar with EDA tools such as OrCAD, Concept HDL, Allegro etc. 12. Good communication skills, English language proficiency

1. 熟悉電子電路設計，具原理圖繪製與PCB Layout協同經驗 2.能獨立規劃與設計 Router、Layer3 Switch、FWA CPE 等網通產品主板 3.了解常見電源架構設計（DC/DC、PoE、LDO 等） 4.具備 EMI/EMC、ESD 設計與除錯經驗 5.能協助產品從 EVB → EVT → DVT → PVT → MP 轉換流程 6. 負責產品驗證及除錯改進及量產可製造性評估 7. 產品維修SOP製作或生產標準的改良方案，以達到在設備性能限制下的最佳品質。 8. 協助驗證電子零件及產品BOM審核 9. 工作態度正向主動積極