「DFT工程師/技術副理」的相似工作

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. SRAM library characterization flow. 2. SRAM library maintaining. 3. Develop and maintain automation flows for analog IC design.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1. Front-end IC design flow development/maintain/support 2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler. 3.Good understanding of timing sign off,constraint and timing closure methodology.

##職務說明 - 相控陣列系統(通訊/雷達)射頻電路(PA/LNA/Mixer/Filter/PLL)架構規劃、模擬及電路設計。 - 根據系統規格進行電子元件評估與選用。 - 與Layout工程師、結構工程師溝通、協調並完成電路、佈局設計及確認 - 電路板及系統層級效能測試、驗證、除錯並將產品導入量產。 - 執行產品研發流程及技術文件產出 ##技能需求 - 具電路 RF / Analog / Digital 電路三年以上設計經驗 - 熟悉量測儀器使用 - 具備基礎焊接能力

【產品線描述】 專注於提供高效能高品質的IC解決方案，涵蓋TV SoC及ASIC領域，並透過深厚的軟體技術優勢，確保產品的市場競爭力。 ■ TV SoC 軟體解決方案： 智慧電視系統整合、影像與音訊處理優化、AI 影像增強、多媒體與串流服務支援 ■ ASIC 軟體解決方案： 高效能低功耗設計、相機與影像處理技術、深度學習推理引擎、高效能計算架構、開發工具鏈 【工作說明】 1. 軟韌體開發 2. 協同客戶開發建構Smart TV 系統 3. 單晶片系統整合 【必要條件】 1. 碩士以上，電子、電機、資工、控制.. 等理/工學院相關科系畢業 2. 具備程式開發能力 3. 能配合工作需求出差

* OSAT (Assembly/Test) 良率異常分析 & 處理。 量產測試驗證，確保量測參數 & 規格符合設計要求。 * 測試結果資料分析，提供良率改善 & 測試流程優化建議。 * CP / FT / SLT 數據追蹤，擬定調整製程參數 or 條件。 測試開發、Debug & 參數優化，提升測試效率 & 良率穩定度。 * 與內部製程/設備/品保單位進行問題分析，釐清異常並提出改善方案。 * 支援測試需求 & 技術交流，確保產品測試時程 & 品質達成量產目標。 1. Co-work w/ functional engineering team member (TME/DE/TD/TE/RE) to make new product has good definition, Risk evaluation and Build comprehensive testing plan / Qual plan, etc. 2. Co-work w/ other Engineering team member to ensure all new product can be thoroughly Manufactured, Characterized and Qualified for reliabilities and qualities. 3. Organize assignments and independently schedules to complete assigned tasks timely and make project finished efficiently. 4. Have good Coordination and Data Analysis to solve difficult problems through application of various techniques and approaches to develop effective and practical solutions that result in improved products, processes with good quality. 5. Co-work with MediaTek - Taiwan Team, and HCLTech - India Team. 6. Annual salary: 800K NTD and above 7. Onsite MediaTek - Hsinchu Science Park Office This position is set for PE (Product Engineer) to coordinate new product development activities, ensure timely completion of all new products manufacturing, testing, characterization, qualification and releasing with good consistency, quality and efficiency. Ref. * CP (Wafer level - Chip Probing) * FT (Packaged chip level - Final Test) * SLT (Packaged chip level - System Level Test) * ATE (Automated Test Equipment)

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1、IC驗證。 2、OLT,ESD,CE/FCC測試。 3、文件整理製作。 4、程式維護。

1. 協助客戶問題釐清及解決, 處理客戶訴願 2. 協助業務推展 3. USB/SATA/PCIe/Ethernet/Serdes電器特性量測

1. FPGA/EVB PCB設計 2. PCIe高速信號PCB設計與量測 3. 與HW/FW跨部門專案合作

(1)Circuit Design. (2)Circuit Simulation. (3)Layout Verification. (4)Silicon verification and debugging. (5)Transfer design to production.

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

1.Integrated verification environment 2.Familiar with SoC level and IP level verification methodology 3.Develop verification plan and optimize verification flow 4.Familiar with verification methodology such as UVM, VMM, or OVM 5.Team player

1. 熟悉數位IC整合流程, 包含RTL模擬 2. 熟悉時序分析及功耗分析流程 3. 有低功耗分析經驗者尤佳 4. 有實體設計經驗者尤佳