「數位IC設計資深工程師/主管」的相似工作

1. Development of ASIC verification plans. 2. Development of UVM tests for ASIC verification to achieve comprehensive coverage. 3. Working with ASIC design and architecture teams to understand functionality. Requirements : 1. Bachelor’s degree in Electrical Engineering or Computer Science. 2. Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred. 3. Knowledge of ARM AMBA Bus protocols 4. Knowledge of System Verilog and UVM verification methodology. 5. Four-year (Master) or six-year (Bachelor) experiences on design verification with UVM platform.

1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 撰寫 Testbench 進行模擬驗證 3. 具 I2C、SPI 通訊介面運作經驗者 4. 熟悉 Xilinx RFSoc 架構與設計 5. 熟悉 Linux Driver 實作經驗

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. Integrate and modify USB2.0 controller IP 2. Solve issues and plan CP/FT of USB projects 3. Design and verify digital circuits.

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1.負責影像處理設計及架構 2.了解ASIC Flow及獨立作業 3.能擔任專案負責人

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

1. 負責數位IC設計整合: a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格 b. 完成SoC系統架構設計，並依功能單元運作屬性區分區塊規格 c. 使用Verilog/VHDL編程內部功能並撰寫RTL code 2. 負責功能驗證與除錯 a. 制定功能驗證計畫 b. 審核驗證計畫的完整性和正確性 c. 進行基本模擬，確認RTL code的功能 d. RTL code寫入FPGA晶片連接系統測試，驗證RTL code 3. 負責時序分析與功耗管理 a. 產出邏輯閘級電路連線網表(netlist) b. 進行SoC系統的時序分析 c. 進行SoC系統的功耗分析 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 三年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 具類比IP整合相關經驗，例如PHY、Serdes、PLL等 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1. Ethernet SerDes高速介面數位設計 (USXGMII, 25G Base-R) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL), 和軟體同仁合作進行相關驗證 3. 具有高速介面或 high level synthesis實作經驗或FPGA實作經驗者尤佳